參數(shù)資料
型號(hào): MCAQE32G8APP-0XA
元件分類: 存儲(chǔ)控制器/管理單元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PQFP
封裝: LQFP
文件頁數(shù): 15/62頁
文件大?。?/td> 740K
代理商: MCAQE32G8APP-0XA
NAND Flash-based Solid State Disk
22
Nov. 15. 2006
The values for the timings for each of the Multiword DMA modes are contained in Table 50.
DMARQ
WRITE
CS0-/CS1-
DD(15:0)
READ
DD(15:0)
Figure 6. Host terminating a Multiword DMA data transfer
DIOR-/DIOW-
DMACK-
t0
tK
tE
tG
tF
tG
tH
(See note 2)
tN
tD
tJ
tZ
NOTE:
1. To terminate the transmission of a data burst, the host shall negate DMACK- within the specified time after a DIOR- or DIOW- pulse. No further
DIOR- or DIOW- pulses shall be asserted for this burst.
2. If the device is able to continue the transfer of data, the Host may leave DMARQ asserted and wait for the host to reassert DMACK- or may negate
DMARQ at any time after detecting that DMACK- has been negated.
(See note 1)
4.6.3.4 Host terminating a Multiword DMA data burst
相關(guān)PDF資料
PDF描述
MC908AZ32AVFU 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PQFP64
MC908AZ32ACFU 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PQFP64
MC908AZ32AMFU 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PQFP64
MC908AZ32AMFUE 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PQFP64
MC908AZ32AVFU 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PQFP64
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