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參數(shù)資料
| 型號： | MCAQE32G8APP-0XA |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PQFP |
| 封裝： | LQFP |
| 文件頁數(shù)： | 42/62頁 |
| 文件大?。?/td> | 740K |
| 代理商： | MCAQE32G8APP-0XA |
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NAND Flash-based Solid State Disk
47
Nov. 15. 2006
5.14.6.1 BSY(Busy)
BSY is set to one to indicate that device is busy. After the host has written the Command Register the device shall have either the
BSY bit set to one, or the DRQ bit set to one, until command completion or the device has performed a bus release for an overlapped
command.
The BSY bit shall be set to one by the device :
1) after either the negation of RESET- or the setting of the SRST bit to one in the Device Control Regitster;
2) after writing the Command Register if the DRQ bit is not set to one;
3) between blocks of a data transfer during PIO data-in commands before the DRQ bit is cleared to zero;
4) After the transfer of a data block during PIO data-out commands before the DRQ bit is cleared to zero;
5) during the data transfer of DMA commands either the BSY bit, the DRQ bit, or both shall be set to one;
NOTE:
The BSY bit may be set to one and then cleared to zero so quickly, that host detection of the BSY bit being set to one is not certain.
When BSY is set to one, the device has control of the Command Block Registers and;
1) a write to a Command Block Register by the host shall be ignored by the device except for writing DEVICE
RESET command;
2) a read from a Command Block register by the host will most likely yield invalid contents except for the BSY bit itself.
The BSY bit shall be cleared to zero by the device:
1)after setting DRQ to one to indicate is ready to transfer data;
2) at command completion;
3) upon releasing the bus for an overlapped command;
4) when the device is ready to accept commands that do not require DRDY during a power on, hardware or software reset.
When BSY is cleared to zero, the host has control of the Command Block registers, the device shall:
1) not set DRQ to one;
2) not change ERR bit;
3) not change the content of any other Command Block Register;
4) set the SERV bit to one when ready to continue an overlapped command that has been bus released.
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