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參數(shù)資料
| 型號： | MCD212 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | Video Decoder and System Controller(with JTAG) |
| 中文描述： | 768 X 560 PIXELS CRT GRPH DSPL CTLR, PQFP160 |
| 封裝： | 1007-01 |
| 文件頁數(shù)： | 16/87頁 |
| 文件大?。?/td> | 872K |
| 代理商： | MCD212 |
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MCD212
2–1
MOTOROLA
“Active” and “inactive” or “asserted” and “negated” are referred to in this user manual independent of
whether the signal is active in the high (logic 1) state or the low (logic 0) state. The definition of the
active level of each signal may be found in the individual pin descriptions.
Mnemonic
Type
Name and Function
A1 – A22
I
System address lines. Provides address for access from the system
bus. Must be stable when UDS and/or LDS are asserted.
Bidirectional data bus, three–state. Used to transfer DATA between
system bus and VDSC. Must be stable when UDS or LDS is
asserted during write access. Driven by VDSC during read cycles.
D0 is the least significant bit.
Upper Data Strobe. Active low. When asserted, UDS indicates that
data is being addressed on D8 to D15.
Lower Data Strobe. Active low. When asserted, LDS indicates that
data is being addressed on D0 to D7.
Read/Write. This input indicates transfer on the system bus. When
low, indicates data is to be written into VDSC controlled resources or
internal registers. When high, indicates a read is taking place.
Chip Select. Active low. When asserted, indicates data transfer
between system bus and VDSC controlled resources is enabled.
Validates address decode for system access.
Data Transfer Acknowledge signal. Active low, three–state. Asserted
by VDSC when the system bus cycle, concerning VDSC controlled
resources, can be continued. This pin must be pulled up externally.
Reset output. Active low, open drain. Asserted by the VDSC reset
sequencer during the reset procedure. This pin must be pulled up
externally.
Halt line output. Active low, open drain. Asserted by the VDSC reset
sequencer during the reset procedure. This pin must be pulled up
externally.
Bus Error output. Active low, three–state. Asserted, when enabled,
by the VDSC watchdog timer circuit if UDS or LDS is still asserted at
the end of the time–out period. This pin must be pulled up externally.
D0 – D15
I/O
UDS
I
LDS
I
R/W
I
CS
I
DTACK
I/O
RSTOUT
O
HALT
O
BERR
O
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