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TABLE OF CONTENTS (Continued)
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Page
Number
Title
Number
MOTOROLA
USERS MANUAL
ix
10.4.2.5
DRAM Controller Control Reg. (DCCR0 - DCCR1) .....10-60
10.5
DRAM Initialization Example ............................................................10-61
Section 11
UART Modules
11.1
Module Overview.................................................................................11-2
11.1.1
Serial Communication Channel.................................................11-2
11.1.2
Baud-Rate Generator/Timer......................................................11-3
11.1.3
Interrupt Control Logic...............................................................11-3
11.2
UART Module Signal Definitions .........................................................11-3
11.2.1
Transmitter Serial Data Output (TxD)........................................11-3
11.2.2
Receiver Serial Data Input (RxD) ..............................................11-4
11.2.3
Request-to-Send (RTS).............................................................11-4
11.2.4
Clear-to-Send (CTS) .................................................................11-4
11.3
Operation.............................................................................................11-5
11.3.1
Baud-Rate Generator/Timer......................................................11-5
11.3.2
Transmitter and Receiver Operating Modes .............................11-6
11.3.2.1
Transmitter.....................................................................11-6
11.3.2.2
Receiver.........................................................................11-9
11.3.2.3
FIFO Stack...................................................................11-11
11.3.3
Looping Modes........................................................................11-12
11.3.3.1
Automatic Echo Mode..................................................11-12
11.3.3.2
Local Loopback Mode..................................................11-12
11.3.3.3
Remote Loopback Mode..............................................11-13
11.3.4
Multidrop Mode........................................................................11-14
11.3.5
Bus Operation .........................................................................11-16
11.3.5.1
Read Cycles ................................................................11-16
11.3.5.2
Write Cycles.................................................................11-16
11.3.5.3
Interrupt Acknowledge Cycles .....................................11-16
11.4
Register Description and Programming ............................................11-16
11.4.1
Register Description ................................................................11-16
11.4.1.1
Mode Register 1 (UMR1).............................................11-17
11.4.1.2
Mode Register 2 (UMR2).............................................11-19
11.4.1.3
Status Register (USR) .................................................11-21
11.4.1.4
Clock Select Register (UCSR).....................................11-24
11.4.1.5
Command Register (UCR)...........................................11-24
11.4.1.6
Receiver Buffer (URB) .................................................11-27
11.4.1.7
Transmitter Buffer (UTB) .............................................11-28
11.4.1.8
Input Port Change Register (UIPCR)...........................11-28
11.4.1.9
Auxiliary Control Register (UACR)...............................11-29
11.4.1.10
Interrupt Status Register (UISR)..................................11-29
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