
TABLE OF CONTENTS (Continued)
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USERS MANUAL
MOTOROLA
14.2.3.4.1
Read A/D Register (RAREG/RDREG) .................................... 14-11
14.2.3.4.2
Write A/D Register (WAREG/WDREG)................................... 14-12
14.2.3.4.3
Read Memory Location (READ).............................................. 14-13
14.2.3.4.4
Write Memory Location (WRITE) ............................................ 14-15
14.2.3.4.5
Dump Memory Block (DUMP)................................................. 14-17
14.2.3.4.6
Fill Memory Block (FILL) ......................................................... 14-20
14.2.3.4.7
Resume Execution (GO) ......................................................... 14-21
14.2.3.4.8
No Operation (NOP)................................................................ 14-22
14.2.3.4.9
Read Control Register (RCREG) ............................................ 14-22
14.2.3.4.10
Write Control Register (WCREG)............................................ 14-24
14.2.3.4.11
Read Debug Module Register (REMREG).............................. 14-24
14.2.3.4.12
Write Debug Module Register (WDMREG) ............................. 14-25
14.2.3.4.13
Unassigned Opcodes.............................................................. 14-26
14.3
Real-Time Debug Support ................................................................ 14-27
14.3.1
Programming Model................................................................ 14-27
14.3.1.1
Address Breakpoint Registers (ABLR, ABHR) ............ 14-28
14.3.1.2
Address Attribute Breakpoint Register (AATR) ........... 14-28
14.3.1.3
Program Counter Breakdown Register (PBR, PBMR) 14-30
14.3.1.4
Data Breakpoint Register (DBR, DBMR)..................... 14-30
14.3.1.5
Trigger Definition Register (TDR) ................................ 14-31
14.3.1.6
Configuration/Status Register (CSR)........................... 14-33
14.3.2
Theory of Operation ................................................................ 14-35
14.3.2.1
Reuse of Debug Module Hardware ............................. 14-37
14.3.3
Concurrent BDM and Processor Operation ............................ 14-37
14.4
Motorola Recommended BDM Pinout............................................... 14-38
14.4.1
Differences Between the ColdFire BDM and a CPU32 BDM.. 14-38
Section 15
IEEE 1149.1 Test Access Port (JTAG)
15.1
Overview ............................................................................................ 15-2
15.2
JTAG Pin Descriptions ....................................................................... 15-2
15.3
JTAG Register Descriptions ............................................................... 15-3
15.3.1
JTAG Instruction Shift Register ............................................... 15-3
15.3.1.1
EXTEST Instruction ...................................................... 15-3
15.3.1.2
ID Code ........................................................................ 15-4
15.3.1.3
SAMPLE/PRELOAD Instruction ................................... 15-4
15.3.1.4
HIGHZ Instruction ......................................................... 15-4
15.3.1.5
CLAMP Instruction ........................................................ 15-5
15.3.1.6
BYPASS Instruction ...................................................... 15-5
15.3.2
ID Code Register ...................................................................... 15-5
15.3.3
JTAG Boundary-Scan Register ................................................ 15-6
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Freescale Semiconductor, Inc.
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