參數(shù)資料
型號: MCF52221CAF66
廠商: Freescale Semiconductor
文件頁數(shù): 15/55頁
文件大?。?/td> 0K
描述: IC MCU 128K FLASH 66MHZ 100-LQFP
標(biāo)準(zhǔn)包裝: 90
系列: MCF5222x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 66MHz
連通性: I²C,SPI,UART/USART,USB OTG
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
配用: M52221DEMO-ND - BOARD DEMO FOR MCF52221
MCF52223 ColdFire Microcontroller, Rev. 3
Family Configurations
Freescale Semiconductor
22
1.6
External Interrupt Signals
Table 9 describes the external interrupt signals.
1.7
Queued Serial Peripheral Interface (QSPI)
Table 10 describes the QSPI signals.
1.8
USB On-the-Go
This device is compliant with industry standard USB 2.0 specification.
1.9
I2C I/O Signals
Table 11 describes the I2C serial interface module signals.
1 The PLL pre-divider (CCHR+1) reset value is 6 and the PLL input reference range is 2–10 MHz,
so in order to boot with the PLL enabled, the external clock or crystal frequency needs to be
greater than 12 MHz. MCF5222x devices cannot boot with PLL enabled from an external clock
or crystal oscillator with frequency less than 12 MHz. This constraint does not apply to booting
with PLL disabled.
2 Cannot boot from the Internal 8 MHz Relaxation oscillator with the PLL enabled. Refer Note1.
Thus this mode has been removed from the table.
Table 9. External Interrupt Signals
Signal Name
Abbreviation
Function
I/O
External Interrupts
IRQ[7:1]
External interrupt sources.
I
Table 10. Queued Serial Peripheral Interface (QSPI) Signals
Signal Name
Abbreviation
Function
I/O
QSPI Synchronous
Serial Output
QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be
driven on the rising or falling edge of QSPI_CLK.
O
QSPI Synchronous
Serial Data Input
QSPI_DIN
Provides the serial data to the QSPI and can be programmed to be
sampled on the rising or falling edge of QSPI_CLK.
I
QSPI Serial Clock
QSPI_CLK
Provides the serial clock from the QSPI. The polarity and phase of
QSPI_CLK are programmable.
O
Synchronous Peripheral
Chip Selects
QSPI_CS[3:0] QSPI peripheral chip select; can be programmed to be active high or
low.
O
Table 11. I2C I/O Signals
Signal Name
Abbreviation
Function
I/O
Serial Clock
SCLn
Open-drain clock signal for the for the I2C interface. When the bus is
In master mode, this clock is driven by the I2C module; when the bus
is in slave mode, this clock becomes the clock input.
I/O
Serial Data
SDAn
Open-drain signal that serves as the data input/output for the I2C
interface.
I/O
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