參數(shù)資料
型號(hào)： MCF52221CAF66
廠商： Freescale Semiconductor
文件頁數(shù)： 28/55頁
文件大?。?/td> 0K
描述： IC MCU 128K FLASH 66MHZ 100-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： MCF5222x
核心處理器： Coldfire V2
芯體尺寸： 32-位
速度： 66MHz
連通性： I²C，SPI，UART/USART，USB OTG
外圍設(shè)備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 56
程序存儲(chǔ)器容量： 128KB（128K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
配用： M52221DEMO-ND - BOARD DEMO FOR MCF52221
Electrical Characteristics
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
34
2.8
Clock Source Electrical Specifications
Table 30. Oscillator and PLL Electrical Specifications
(VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V)
Characteristic
Symbol
Min
Max
Unit
Clock Source Frequency Range of EXTAL Frequency Range
Crystal
External1
1 In external clock mode, it is possible to run the chip directly from an external clock source without enabling the PLL.
fcrystal
fext
1
0
25.02
66.67 or 80
2 This value has been updated.
MHz
PLL reference frequency range
fref_pll
210.0
MHz
System frequency 3
External clock mode
On-chip PLL frequency
3 All internal registers retain data at 0 Hz.
fsys
0
fref / 32
66.67 or 804
66.67 or 804
4 Depending on packaging; see the orderable part number summary.
MHz
Loss of reference frequency 5, 7
5 Loss of Reference Frequency is the reference frequency detected internally, which transitions the PLL into self clocked mode.
fLOR
100
1000
kHz
Self clocked mode frequency 6
6 Self clocked mode frequency is the frequency at which the PLL operates when the reference frequency falls below f
LOR with
default MFD/RFD settings.
fSCM
15
MHz
Crystal start-up time 7, 8
7 This parameter is characterized before qualification rather than 100% tested.
8 Proper PC board layout procedures must be followed to achieve specifications.
tcst
—10
ms
EXTAL input high voltage
External reference
VIHEXT
2.0
V
EXTAL input low voltage
External reference
VILEXT
VSS
0.8
V
PLL lock time4,9
9 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
tlpll
—500
s
Duty cycle of reference 4
tdc
40
60
% fref
Frequency un-LOCK range
fUL
–1.5
1.5
% fref
Frequency LOCK range
fLCK
–0.75
0.75
% fref
CLKOUT period jitter 4, 5, 10 ,11, measured at fSYS Max
Peak-to-peak (clock edge to clock edge)
Long term (averaged over 2 ms interval)
10 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the Cjitter percentage
for a given interval.
11 Based on slow system clock of 40 MHz measured at f
sys max.
Cjitter
—
10
.01
% fsys
On-chip oscillator frequency
foco
7.84
8.16
MHz
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MCF52223_07 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ColdFire Microcontroller
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