參數(shù)資料
型號(hào): MCF52232CAF50
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 28/55頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT 128K FLASH 80-LQFP
標(biāo)準(zhǔn)包裝: 90
系列: MCF5223x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 50MHz
連通性: 以太網(wǎng),I²C,SPI,UART/USART
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲(chǔ)器容量: 128KB(128K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-LQFP
包裝: 托盤
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10
Electrical Characteristics
Freescale Semiconductor
34
2.4
Phase Lock Loop Electrical Specifications
Table 25. Oscillator and PLL Electrical Specifications
(VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V)
Characteristic
Symbol
Min
Max
Unit
Clock Source Frequency Range of EXTAL Frequency Range
Crystal
External1
1 In external clock mode, it is possible to run the chip directly from an external clock source without enabling the PLL.
fcrystal
fext
0.5
0
25.0
60.0
MHz
PLL reference frequency range
fref_pll
210.0
MHz
System frequency 2
External clock mode
On-Chip PLL Frequency
2
All internal registers retain data at 0 Hz.
fsys
0
fref / 32
60
MHz
Loss of reference frequency 3, 5
3 Loss of reference frequency is the reference frequency detected internally that transitions the PLL into self-clocked mode.
fLOR
100
1000
kHz
Self clocked mode frequency 4, 5
4 Self-clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f
LOR with
default MFD/RFD settings.
fSCM
15
MHz
Crystal start-up time 5, 6
5 This parameter is characterized before qualification rather than 100% tested.
6 Proper PC board layout procedures must be followed to achieve specifications.
tcst
—10
ms
EXTAL input high voltage
Crystal reference
External reference
VIHEXT
VDD- 1.0
2.0
VDD
3.07
V
EXTAL input low voltage
Crystal reference
External reference
VILEXT
VSS
1.0
0.8
V
XTAL output high voltage
IOH = 1.0 mA
VOL
VDD –1.0
V
XTAL output low voltage
IOL = 1.0 mA
VOL
—0.5
V
XTAL load capacitance8
——
pF
PLL lock time5,9
tlpll
—500
s
Power-up to lock time 5, 7,9
With crystal reference
Without crystal reference
tlplk
10.5
500
ms
s
Duty cycle of reference 5
tdc
40
60
% fsys
Frequency un-LOCK range
fUL
–1.5
1.5
% fsys
Frequency LOCK range
fLCK
–0.75
0.75
% fsys
CLKOUT period Jitter 5, 6, 8, 10,11, measured at fSYS Max
Peak-to-peak jitter (clock edge to clock edge)
Long term jitter (averaged over 2 ms interval)
Cjitter
10
0.01
% fsys
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