參數(shù)資料
型號(hào): MCF52232CAF50
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 30/55頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT 128K FLASH 80-LQFP
標(biāo)準(zhǔn)包裝: 90
系列: MCF5223x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 50MHz
連通性: 以太網(wǎng),I²C,SPI,UART/USART
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲(chǔ)器容量: 128KB(128K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-LQFP
包裝: 托盤
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10
Electrical Characteristics
Freescale Semiconductor
36
2.6
Reset Timing
Figure 7. RSTI and Configuration Override Timing
2.7
I2C Input/Output Timing Specifications
Table 28 lists specifications for the I2C input timing parameters shown in Figure 8.
Table 29 lists specifications for the I2C output timing parameters shown in Figure 8.
Table 27. Reset and Configuration Override Timing
(VDD = 2.7 to 3.6 V, VSS = 0 V, T
A
= TL to TH)
1
1 All AC timing is shown with respect to 50% V
DD levels unless otherwise noted.
Num
Characteristic
Symbol
Min
Max
Unit
R1
RSTI input valid to CLKOUT high
tRVCH
9—
ns
R2
CLKOUT high to RSTI input invalid
tCHRI
1.5
ns
R3
RSTI input valid time 2
2 During low power STOP, the synchronizers for the RSTI input are bypassed and RSTI is asserted asynchronously to the
system. Therefore, RSTI must be held a minimum of 100ns.
tRIVT
5—
tCYC
R4
CLKOUT high to RSTO valid
tCHROV
—10
ns
Table 28. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I1
Start condition hold time
2
t
CYC
—ns
I2
Clock low period
8
t
CYC
—ns
I3
SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
1
ms
I4
Data hold time
0
ns
I5
SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
1
ms
I6
Clock high time
4
t
CYC
—ns
I7
Data setup time
0
ns
I8
Start condition setup time (for repeated start condition only)
2
t
CYC
—ns
I9
Stop condition setup time
2
t
CYC
—ns
1R1
R2
CLKOUT
RSTI
RSTO
R3
R4
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