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參數(shù)資料
型號(hào): MCF52232CAF50
廠商: Freescale Semiconductor
文件頁數(shù): 3/55頁
文件大小: 0K
描述: IC MCU 32BIT 128K FLASH 80-LQFP
標(biāo)準(zhǔn)包裝: 90
系列: MCF5223x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 50MHz
連通性: 以太網(wǎng),I²C,SPI,UART/USART
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲(chǔ)器容量: 128KB(128K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-LQFP
包裝: 托盤
MCF52235 Family Configurations
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10
Freescale Semiconductor
11
1.2.10
I2C Bus
The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange and minimizes the
interconnection between devices. This bus is suitable for applications requiring occasional communications over a short
distance between many devices on a circuit board.
1.2.11
QSPI
The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with queued transfer capability.
It allows up to 16 transfers to be queued at once, minimizing the need for CPU intervention between transfers.
1.2.12
Fast ADC
The Fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold (S/H) circuits feeding
separate 10- or 12-bit ADCs. The two separate converters store their results in accessible buffers for further processing.
The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or perform a programmed
scan sequence repeatedly until manually stopped.
The ADC can be configured for sequential or simultaneous conversion. When configured for sequential conversions, up to eight
channels can be sampled and stored in any order specified by the channel list register. Both ADCs may be required during a
scan, depending on the inputs to be sampled.
During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same time. This
configuration requires that a single channel may not be sampled by both S/H circuits simultaneously.
Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low
threshold limit or above the high threshold limit set in the limit registers) or at several different zero crossing conditions.
1.2.13
DMA Timers (DTIM0–DTIM3)
There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3) on the each device.
Each module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured
to operate from the system clock or from an external clock source using one of the DTINx signals. If the system clock is selected,
it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual
timer counter register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode.
Timer events may optionally cause interrupt requests or DMA transfers.
1.2.14
General Purpose Timer (GPT)
The general purpose timer (GPT) is a 4-channel timer module consisting of a 16-bit programmable counter driven by a 7-stage
programmable prescaler. Each of the four channels can be configured for input capture or output compare. Additionally, one of
the channels, channel 3, can be configured as a pulse accumulator.
A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter.
The input capture and output compare functions allow simultaneous input waveform measurements and output waveform
generation. The input capture function can capture the time of a selected transition edge. The output compare function can
generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a
gated time accumulator.
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