參數(shù)資料
型號(hào): MCF52235
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: ColdFire Microcontroller
中文描述: ColdFire微控制器
文件頁數(shù): 37/50頁
文件大?。?/td> 656K
代理商: MCF52235
Preliminary Electrical Characteristics
MCF52235 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
37
Figure 8
shows timing for the values in
Table 28
and
Table 29
.
Figure 8. I
2
C Input/Output Timings
Table 29. I
2
C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I1
1
Start condition hold time
6
×
t
CYC
10
×
t
CYC
ns
I2
1
Clock low period
ns
I3
2
I2C_SCL/I2C_SDA rise time
(V
IL
= 0.5 V to V
IH
= 2.4 V)
μs
I4
1
Data hold time
7
×
t
CYC
ns
I5
3
I2C_SCL/I2C_SDA fall time
(V
IH
= 2.4 V to V
IL
= 0.5 V)
3
ns
I6
1
Clock high time
10
×
t
CYC
2
×
t
CYC
ns
I7
1
Data setup time
ns
I8
1
Start condition setup time (for repeated start
condition only)
20 x t
CYC
ns
I9
1
Stop condition setup time
10 x t
CYC
ns
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in
Table 29
. The I
2
C
interface is designed to scale the actual data transition time to move it to the middle of the SCL low
period. The actual position is affected by the prescale and division values programmed into the IFDR;
however, the numbers given in
Table 29
are minimum values.
2
Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive
low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
3
Specified at a nominal 50-pF load.
I2
I6
I1
I4
I7
I8
I9
I5
I3
SCL
SDA
相關(guān)PDF資料
PDF描述
MCF5232CAB80 Integrated Microprocessor Hardware Specification
MCF5232 Integrated Microprocessor Hardware Specification
MCF5249 CodeWarrior Development Studio for ColdFire㈢ Architectures
MCF5251_07 ColdFire㈢ Microprocessor Data Sheet
MCF5251 ColdFire Processor
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