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參數(shù)資料
| 型號： | MCF52277CVM166 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 166.67 MHz, RISC PROCESSOR, PBGA196 |
| 封裝： | 15 X 15 MM, PLASTIC, ROHS COMPLIANT, MAPBGA-196 |
| 文件頁數(shù)： | 7/42頁 |
| 文件大?。?/td> | 1632K |
| 代理商： | MCF52277CVM166 |
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Electrical Characteristics
MCF5227x ColdFire Microprocessor Data Sheet, Rev. 4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
15
5.2
Thermal Characteristics
The average chip-junction temperature (TJ) in °C can be obtained from:
Eqn. 1
Where:
TA
= Ambient Temperature, °C
QJMA
= Package Thermal Resistance, Junction-to-Ambient, °C/W
PD
=PINT + PI/O
PINT
=IDD × IVDD, Watts - Chip Internal Power
PI/O
= Power Dissipation on Input and Output Pins — User Determined
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:
Eqn. 2
Solving equations 1 and 2 for K gives:
Eqn. 3
Table 6. Thermal Characteristics
Characteristic
Symbol
196
MAPBGA
176
LQFP
Unit
Junction to ambient, natural convection
Four layer board
(2s2p)
θ
JMA
471,2
1
θ
JMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.
Freescale recommends the use of
θ
JmA and power dissipation specifications in the system design to prevent
device junction temperatures from exceeding the rated specification. System designers should be aware that
device junction temperatures can be significantly influenced by board layout and surrounding devices.
Conformance to the device junction temperature specification can be verified by physical measurement in the
customer’s system using the
Ψ
jt parameter, the device power dissipation, and the method described in
EIA/JESD Standard 51-2.
2 Per JEDEC JESD51-6 with the board horizontal.
TBD
°C/W
Junction to ambient (@200 ft/min)
Four layer board
(2s2p)
θ
JMA
431,2
TBD
°C/W
Junction to board
θ
JB
363
3 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
TBD
°C/W
Junction to case
θ
JC
224
4 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
TBD
°C/W
Junction to top of package
Ψ
jt
61,5
5 Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written in conformance with Psi-JT.
TBD
°C/W
Maximum operating junction temperature
Tj
105
TBD
oC
TJ
TA
PD ΘJMA
×
()
+
=
PD
K
TJ 273°C
+
()
---------------------------------
=
KPD
TA 273°C
×
() Q
JMA
PD
2
×
+
×
=
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