參數(shù)資料
型號(hào): MCF5275CVM166
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 17/44頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT 166MHZ 256-MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: MCF527x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 166MHz
連通性: EBI/EMI,以太網(wǎng),I²C,SPI,UART/USART,USB
外圍設(shè)備: DMA,WDT
輸入/輸出數(shù): 69
程序存儲(chǔ)器類型: ROMless
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.4 V ~ 1.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 散裝
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor
24
8.6
External Interface Timing Characteristics
Table 12 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the CLKOUT output.
All other timing relationships can be derived from these values.
4
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below
fLOR with default MFD/RFD settings.
5
This parameter is guaranteed by characterization before qualification rather than 100% tested.
6
Proper PC board layout procedures must be followed to achieve specifications.
7
Load capacitance determined from crystal manufacturer specifications and includes circuit board parasitics.
8
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
9
Assuming a reference is available at power up, lock time is measured from the time VDD and VDDPLL are valid to
RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time
must be added to the PLL lock time to determine the total start-up time.
10 t
lpll = (64 * 4 * 5 + 5 x τ) x Tref, where Tref = 1/Fref_crystal = 1/Fref_ext = 1/Fref_1:1, and τ = 1.57x10
-6 x 2(MFD + 2)
11 PLL is operating in 1:1 PLL mode.
12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fsys/2. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the jitter percentage for a given interval.
13 Based on slow system clock of 33MHz maximum frequency.
14 Modulation percentage applies over an interval of 10
μs, or equivalently the modulation rate is 100KHz.
15 Modulation rate selected must not result in f
sys/2 value greater than the fsys/2 maximum specified value. Modulation
range determined by hardware design.
16 f
sys/2 = fico / (2 * 2
RFD)
Table 12. Processor Bus Input Timing Specifications
Name
Characteristic1
1
Timing specifications have been indicated taking into account the full drive strength for the pads.
Symbol
Min
Max
Unit
B0
CLKOUT
tCYC
12
ns
Control Inputs
B1a
Control input valid to CLKOUT high2
2
TEA and TA pins are being referred to as control inputs.
tCVCH
9—
ns
B1b
BKPT valid to CLKOUT high3
3
Refer to figure A-19.
tBKVCH
9—
ns
B2a
CLKOUT high to control inputs invalid2
tCHCII
0—
ns
B2b
CLKOUT high to asynchronous control input BKPT invalid3
tBKNCH
0—
ns
Data Inputs
B4
Data input (D[31:16]) valid to CLKOUT high
tDIVCH
4—
ns
B5
CLKOUT high to data input (D[31:16]) invalid
tCHDII
0—
ns
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