參數(shù)資料
型號(hào): MCF53016CMJ240J
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 18/62頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT 128KB 256MAPBGA
標(biāo)準(zhǔn)包裝: 450
系列: MCF5301x
核心處理器: Coldfire V3
芯體尺寸: 32-位
速度: 240MHz
連通性: EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,PWM,WDT
輸入/輸出數(shù): 83
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 緩存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.08 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-LBGA
包裝: 托盤(pán)
Preliminary Electrical Characteristics
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
25
5.6
External Interface Timing Characteristics
Table 12 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and output delay with
respect to the rising edge of a reference clock. The reference clock is the FB_CLK output.
All other timing relationships can be derived from these values. Timings listed in Table 12
are shown in Figure 11 and Figure 12.
Figure 10. General Input Timing Requirements
5.6.1
FlexBus
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up
to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such as external
boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For
asynchronous devices a simple chip-select based interface can be used. The FlexBus interface has six general purpose
chip-selects (FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory interfaces.
8
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.
9
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod.
10 Modulation percentage applies over an interval of 10
μs, or equivalently the modulation rate is 100kHz.
11 Modulation range determined by hardware design.
Invalid
FB_CLK (80MHz)
TSETUP
THOLD
Input Setup And Hold
1.5V
trise
Vh = VIH
Vl = VIL
1.5V
Valid
tfall
Vh = VIH
Vl = VIL
Input Rise Time
Input Fall Time
* The timings are also valid for inputs sampled on the negative clock edge.
Inputs
FB_CLK
B4
B5
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