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參數(shù)資料
| 型號： | MCF53016CMJ240J |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 21/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 128KB 256MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 450 |
| 系列： | MCF5301x |
| 核心處理器： | Coldfire V3 |
| 芯體尺寸： | 32-位 |
| 速度： | 240MHz |
| 連通性： | EBI/EMI，以太網(wǎng)，I²C，MMC，SPI，SSI，UART/USART，USB，USB OTG |
| 外圍設(shè)備： | DMA，PWM，WDT |
| 輸入/輸出數(shù)： | 83 |
| 程序存儲器容量： | 16KB（16K x 8） |
| 程序存儲器類型： | 緩存 |
| RAM 容量： | 128K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.08 V ~ 3.6 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 256-LBGA |
| 包裝： | 托盤 |
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MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Preliminary Electrical Characteristics
Freescale Semiconductor
28
read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SD_SDR_DQS signal and its usage.
Table 13. SDR Timing Specifications
Symbol
Characteristic
Symbol
Min
Max
Unit
Notes
Frequency of operation
50
80
Mhz
1
The device supports same frequency of operation for both FlexBus and SDRAM clock operates as that of the internal bus clock.
Please see the PLL chapter of the MCF5301x Reference Manual for more information on setting the SDRAM clock rate.
SD1
Clock period
tSDCK
12.5
20
ns
2
SD_CLK is one SDRAM clock in (ns).
SD2
Pulse width high
tSDCKH
0.45
0.55
SD_CLK
3
Pulse width high plus pulse width low cannot exceed min and max clock period.
SD3
Pulse width low
tSDCKH
0.45
0.55
SD_CLK
4
Pulse width high plus pulse width low cannot exceed min and max clock period.
SD4
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] output valid
tSDCHACV
—0.5
× SD_CLK
+1.0
ns
SD5
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] output hold
tSDCHACI
2.0
—
ns
SD6
SD_SDR_DQS output valid
tDQSOV
—
Self timed
ns
5
SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation
from this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data beat.
SD7
SD_DQS[3:0] input setup relative to SD_CLK
tDQVSDCH
0.25
×
SD_CLK
0.40
× SD_CLK
ns
6
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each data
beat.
SD8
SD_DQS[3:2] input hold relative to SD_CLK
tDQISDCH
Does not apply. 0.5
×SD_CLK fixed
width.
7
The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does
not affect the memory controller.
SD9
Data (D[31:0]) input setup relative to SD_CLK (reference
only)
tDVSDCH
0.25
×
SD_CLK
—ns
8
Since a read cycle in SDR mode still uses the DQS circuit within the device, it is most critical that the data valid window be
centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup
spec is just provided as guidance.
SD10
Data input hold relative to SD_CLK (reference only)
tDISDCH
1.0
—
ns
SD11
Data (D[31:0]) and data mask (SD_DQM[3:0]) output valid
tSDCHDMV
—0.75
× SD_CLK
+ 0.5
ns
SD12
Data (D[31:0]) and data mask (SD_DQM[3:0]) output hold
tSDCHDMI
1.5
—
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCF53017 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Version 3 ColdFire? core with EMAC |
| MCF53017_10 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Version 3 ColdFire? core with EMAC |
| MCF53017CMJ240 | 制造商:Freescale Semiconductor 功能描述:LONGJING C&I CFV3 VOIP+S - Bulk 制造商:Rochester Electronics LLC 功能描述: |
| MCF53017CMJ240J | 功能描述:32位微控制器 - MCU CFV3 SEC&VOIP RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MCF5307 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:UART MODULE |
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