參數(shù)資料
型號(hào)： MCF53016CMJ240J
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 24/62頁(yè)
文件大?。?/td> 0K
描述： IC MCU 32BIT 128KB 256MAPBGA
標(biāo)準(zhǔn)包裝： 450
系列： MCF5301x
核心處理器： Coldfire V3
芯體尺寸： 32-位
速度： 240MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，MMC，SPI，SSI，UART/USART，USB，USB OTG
外圍設(shè)備： DMA，PWM，WDT
輸入/輸出數(shù)： 83
程序存儲(chǔ)器容量： 16KB（16K x 8）
程序存儲(chǔ)器類型： 緩存
RAM 容量： 128K x 8
電壓 - 電源 (Vcc/Vdd)： 1.08 V ~ 3.6 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 256-LBGA
包裝： 托盤
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Preliminary Electrical Characteristics
Freescale Semiconductor
30
5.7.2
DDR SDRAM AC Timing Characteristics
When the SDRAM controller is configured for DDR SDRAM, the following timing numbers must be followed to properly latch
or drive data onto the memory bus. All timing numbers are relative to the four DQS byte lanes. The following timing numbers
are subject to change at anytime, and are only provided to aid in early board design.
Table 14. DDR Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
Notes
Frequency of Operation
tDDCK
50
80
Mhz
1
1 The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the
same frequency as the internal bus clock.
DD1
Clock Period
tDDSK
12.5
20
ns
2
2 SD_CLK is one SDRAM clock in (ns).
DD2
Pulse Width High
tDDCKH
0.45
0.55
SD_CLK
3
3 Pulse width high plus pulse width low cannot exceed min and max clock period.
DD3
Pulse Width Low
tDDCKL
0.45
0.55
SD_CLK
DD4
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] Output Valid
tSDCHACV
—0.5
× SD_CLK
+1.0
ns
4
4 Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature,
and voltage variations.
DD5
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] Output Hold
tSDCHACI
2.0
—
ns
DD6
Write Command to first DQS Latching Transition
tCMDVDQ
—
1.25
SD_CLK
DD7
Data and Data Mask Output Setup (DQ-->DQS)
Relative to DQS (DDR Write Mode)
tDQDMV
1.5
—
ns
5
6
5 This specification relates to the required input setup time of today’s DDR memories. The device’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.
SD_D[31:24] is relative to SD_DQS3, SD_D[23:16] is relative to SD_DQS2, SD_D[15:8] is relative to SD_DQS1, and
SD_D[7:0] is relative SD_DQS0.
6 The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats
will be valid for each subsequent DQS edge.
DD8
Data and Data Mask Output Hold (DQS-->DQ)
Relative to DQS (DDR Write Mode)
tDQDMI
1.0
—
ns
7
7 This specification relates to the required hold time of today’s DDR memories. SD_D[31:24] is relative to SD_DQS3,
SD_D[23:16] is relative to SD_DQS2, SD_D[15:8] is relative to SD_DQS1, and SD_D[7:0] is relative SD_DQS0.
DD9
Input Data Skew Relative to DQS (Input Setup)
tDVDQ
—1
ns
8
DD10 Input Data Hold Relative to DQS.
tDIDQ
0.25
× SD_CLK
+0.5ns
—ns
9
DD11 DQS falling edge from SDCLK rising (output hold time) tDQLSDCH
0.5
—
ns
DD12 DQS input read preamble width
tDQRPRE
0.9
1.1
SD_CLK
DD13 DQS input read postamble width
tDQRPST
0.4
0.6
SD_CLK
DD14 DQS output write preamble width
tDQWPRE
0.25
—
SD_CLK
DD15 DQS output write postamble width
tDQWPST
0.4
0.6
SD_CLK
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