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參數(shù)資料
| 型號： | MCF5485CZP200 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 1/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT COLDF 388-PBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | MCF548x |
| 核心處理器： | Coldfire V4E |
| 芯體尺寸： | 32-位 |
| 速度： | 200MHz |
| 連通性： | CAN，EBI/EMI，以太網(wǎng)，I²C，SPI，UART/USART，USB |
| 外圍設(shè)備： | DMA，PWM，WDT |
| 輸入/輸出數(shù)： | 99 |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.43 V ~ 1.58 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 388-BBGA |
| 包裝： | 托盤 |
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Freescale Semiconductor
Data Sheet
Document Number: MCF5485EC
Rev. 4, 12/2007
Freescale Semiconductor, Inc., 2007. All rights reserved.
MCF548x
TEPBGA–388
27 mm x 27 mm
Features list:
ColdFire V4e Core
– Limited superscalar V4 ColdFire processor core
– Up to 200MHz peak internal core frequency (308 MIPS
[Dhrystone 2.1] @ 200 MHz)
– Harvard architecture
– 32-Kbyte instruction cache
– 32-Kbyte data cache
– Memory Management Unit (MMU)
– Separate, 32-entry, fully-associative instruction and
data translation lookahead buffers
– Floating point unit (FPU)
– Double-precision conforms to IEE-754 standard
– Eight floating point registers
Internal master bus (XLB) arbiter
– High performance split address and data transactions
– Support for various parking modes
32-bit double data rate (DDR) synchronous DRAM
(SDRAM) controller
– 66–133 MHz operation
– Supports DDR and SDR DRAM
– Built-in initialization and refresh
– Up to four chip selects enabling up to one GB of external
memory
Version 2.2 peripheral component interconnect (PCI) bus
– 32-bit target and initiator operation
– Support for up to five external PCI masters
– 33–66 MHz operation with PCI bus to XLB divider
ratios of 1:1, 1:2, and 1:4
Flexible multi-function external bus (FlexBus)
– Provides a glueless interface to boot flash/ROM,
SRAM, and peripheral devices
– Up to six chip selects
– 33 – 66 MHz operation
Communications I/O subsystem
– Intelligent 16 channel DMA controller
– Up to two 10/100 Mbps fast Ethernet controllers (FECs)
each with separate 2-Kbyte receive and transmit FIFOs
– Universal serial bus (USB) version 2.0 device controller
– Support for one control and six programmable
endpoints, interrupt, bulk, or isochronous
– 4-Kbytes of shared endpoint FIFO RAM and 1 Kbyte
of endpoint descriptor RAM
– Integrated physical layer interface
– Up to four programmable serial controllers (PSCs) each
with separate 512-byte receive and transmit FIFOs for
UART, USART, modem, codec, and IrDA 1.1 interfaces
–I2C peripheral interface
– Two FlexCAN controller area network 2.0B controllers
each with 16 message buffers
– DMA Serial Peripheral Interface (DSPI)
Optional Cryptography accelerator module
– Execution units for:
– DES/3DES block cipher
– AES block cipher
– RC4 stream cipher
– MD5/SHA-1/SHA-256/HMAC hashing
– Random Number Generator
32-Kbyte system SRAM
– Arbitration mechanism shares bandwidth between
internal bus masters
System integration unit (SIU)
– Interrupt controller
– Watchdog timer
– Two 32-bit slice timers alarm and interrupt generation
– Up to four 32-bit general-purpose timers, compare, and
PWM capability
– GPIO ports multiplexed with peripheral pins
Debug and test features
– ColdFire background debug mode (BDM) port
– JTAG/ IEEE 1149.1 test access port
PLL and clock generator
– 30 to 66.67 MHz input frequency range
Operating Voltages
– 1.5V internal logic
– 2.5V DDR SDRAM bus I/O
– 3.3V PCI, FlexBus, and all other I/O
Estimated power consumption
– Less than 1.5W (388 PBGA)
MCF548x ColdFire
Microprocessor
Supports MCF5480, MCF5481,
MCF5482, MCF5483, MCF5484, and
MCF5485
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