MCF548x ColdFire Microprocessor, Rev. 4 Fast Ethernet AC Timing Specifications F" />
參數(shù)資料
型號(hào)： MCF5485CZP200
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 15/34頁(yè)
文件大小： 0K
描述： IC MPU 32BIT COLDF 388-PBGA
標(biāo)準(zhǔn)包裝： 40
系列： MCF548x
核心處理器： Coldfire V4E
芯體尺寸： 32-位
速度： 200MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，I²C，SPI，UART/USART，USB
外圍設(shè)備： DMA，PWM，WDT
輸入/輸出數(shù)： 99
程序存儲(chǔ)器類(lèi)型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.43 V ~ 1.58 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 388-BBGA
包裝： 托盤(pán)
MCF548x ColdFire Microprocessor, Rev. 4
Fast Ethernet AC Timing Specifications
Freescale Semiconductor
22
Figure 18. PCI Timing
11
Fast Ethernet AC Timing Specifications
11.1
MII/7-WIRE Interface Timing Specs
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the EMAC_10_100 I/O signals.
The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices. If this
interface is to be used with a specific transceiver device the timing specs may be altered to match that specific transceiver.
P7
PCI signals (0–50 Mhz) - Input Hold (tIH)0
—
ns
5
P8
PCI REQ/GNT (33
< PCI ≤ 50Mhz) - Output valid (t
DV)—
6
ns
6
P9
PCI REQ/GNT (0
< PCI ≤ 33Mhz) - Output valid (t
DV)
—
12
ns
P10
PCI REQ/GNT (33
< PCI ≤ 50Mhz) - Input Setup (t
IS)—
5
ns
P11
PCI REQ (0
< PCI ≤ 33Mhz) - Input Setup (t
IS)12
—
ns
P12
PCI GNT (0
< PCI ≤ 33Mhz) - Input Setup (t
IS)10
—
ns
1 Please see the reset configuration signals description in the “Signal Descriptions” chapter within the MCF548x
Reference Manual. Also specific guidelines may need to be followed when operating the system PLL below certain
frequencies.
2 Max cycle rate is determined by CLKIN and how the user has the system PLL configured.
3 All signals defined as PCI bused signals. Does not include PTP (point-to-point) signals.
4 PCI 2.2 spec does not require an output hold time. Although the MCF548X may provide a slight amount of hold, it
is not required or guaranteed.
5 PCI 2.2 spec requires zero input hold.
6 These signals are defined at PTP (Point-to-point) in the PCI 2.2 spec.
Table 14. PCI Timing Specifications (continued)
Num
Characteristic
Min
Max
Unit
Notes
CLKIN
Input
Setup/Hold
P1
P4
P6
P2
P7
Output Valid
Input Valid
Output
Valid/Hold
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