參數(shù)資料
型號: MCIMX251AJM4A
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA400
封裝: 17 X 17 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-400
文件頁數(shù): 111/140頁
文件大?。?/td> 1416K
代理商: MCIMX251AJM4A
i.MX25 Applications Processor for Automotive Products, Rev. 8
72
Freescale Semiconductor
NOTE
The test condition load capacitance was 25 pF. Recommended drive
strength for all controls, address, and BCLK is maximum drive.
Recommended drive strength for all controls, address and BCLK is
maximum drive.
WE8
Clock rise/fall to RW_B valid
8
12
ns
WE9
Clock rise/fall to RW_B invalid
3
8
ns
WE10
Clock rise/fall to OE_B valid
7
12
ns
WE11
Clock rise/fall to OE_B invalid
3.6
5.5
ns
WE12
Clock rise/fall to EBy_B valid
6
11.5
ns
WE13
Clock rise/fall to EBy_B invalid
6
10
ns
WE14
Clock rise/fall to LBA_B valid
17.5
20
ns
WE15
Clock rise/fall to LBA_B invalid
0
1
ns
WE16
Clock rise/fall to output data valid
5
10
ns
WE17
Clock rise to output data invalid
0
2.5
ns
WE18
Input data valid to clock rise, FCE=1
1
ns
WE19
Input Data Valid to Clock rise, FCE=0 (in the case there is ECB_B asserted
during access)
1/2 BCLK
+2.63
—ns
Input Data Valid to Clock rise, FCE=0 (in the case there is NO ECB_B asserted
during access)
6.9
ns
WE20
Clock rise to input data invalid, FCE=1
1
ns
WE21
Clock rise to input data invalid, FCE=0
2.4
ns
WE22
ECB_B setup time, FCE=1
5
ns
WE23
ECB_B setup time, FCE=0
7.2
ns
WE24
ECB_B hold time, FCE=1
5
ns
WE25
ECB_B hold time, FCE=0
0
ns
WE26
DTACK_B setup time
5.4
ns
WE27
DTACK_B hold time
–3.2
ns
1 High is defined as 80% of signal value; low is defined as 20% of signal value.
2 BCLK parameters are being measured from the 50% point. For example, high is defined as 50% of signal value and low is
defined as 50% as signal value.
Table 56. WEIM Bus Timing Parameters1 (continued)
ID
Parameter
Min.
Max.
Unit
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