參數(shù)資料
型號(hào): MCIMX251AJM4A
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA400
封裝: 17 X 17 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-400
文件頁數(shù): 139/140頁
文件大小: 1416K
代理商: MCIMX251AJM4A
i.MX25 Applications Processor for Automotive Products, Rev. 8
98
Freescale Semiconductor
3.7.14.1
SIM Reset Sequences
SIM cards may have internal reset, or active low reset. The following subset describes the reset sequences
in these two cases.
3.7.14.1.1
SIM Cards with Internal Reset
Figure 69 shows the reset sequence for SIM cards with internal reset. The reset sequence comprises the
following steps:
After power-up, the clock signal is enabled on SIMx_CLKy (time T0)
After 200 clock cycles, SIMx_DATAy_RX_TX must be asserted.
The card must send a response on SIMx_DATAy_RX_TX acknowledging the reset between
400–40000 clock cycles after T0.
Figure 69. Internal Reset Card Reset Sequence
Table 75 defines the general timing requirements for the SIM interface.
3.7.14.1.2
SIM Cards with Active Low Reset
Figure 70 shows the reset sequence for SIM cards with active low reset. The reset sequence comprises the
following steps:
After power-up, the clock signal is enabled on SIMx_CLKy (time T0)
After 200 clock cycles, SIMx_DATAy_RX_TX must be asserted.
SIMx_RSTy must remain low for at least 40,000 clock cycles after T0 (no response is to be received
on RX during those 40,000 clock cycles)
SIMx_RSTy is asserted (at time T1)
SIMx_RSTy must remain asserted for at least 40,000 clock cycles after T1, and a response must be
received on SIMx_DATAy_RX_TX between 400 and 40,000 clock cycles after T1.
Table 75. Timing Specifications, Internal Reset Card Reset Sequence
Ref No.
Min.
Max.
Units
1
200
clk cycles
2
400
40,000
clk cycles
SIMn_SVENm
SIMx_CLKy
SIMx_DATAy_RX_TX
2
T0
RESPONSE
1
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