參數(shù)資料
型號: MCIMX257CVM4
廠商: Freescale Semiconductor
文件頁數(shù): 149/153頁
文件大?。?/td> 0K
描述: IC MPU I.MX25 IND 400MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: i.MX25
核心處理器: ARM9
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 128
程序存儲器類型: 外部程序存儲器
RAM 容量: 144K x 8
電壓 - 電源 (Vcc/Vdd): 1.15 V ~ 1.52 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 400-LFBGA
包裝: 托盤
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor
95
Figure 67. PWM Timing
3.7.14
Subscriber Identity Module (SIM) Timing
Each SIM module interface consists of a total of 12 pins (two separate ports, each containing six signals).
Typically a port uses five signals.
The interface is designed to be used with synchronous SIM cards, meaning the SIM module provides the
clock used by the SIM card. The clock frequency is typically 372 times the Tx/Rx data rate; however, the
SIM module can also work with CLK frequencies of 16 times the Tx/Rx data rate.
There is no timing relationship between the clock and the data. The clock that the SIM module provides
to the SIM card is used by the SIM card to recover the clock from the data in the same manner as standard
UART data exchanges. All six signals (five for bidirectional Tx/Rx) of the SIM module are asynchronous
with each other.
There are no required timing relationships between signals in normal mode. The SIM card is initiated by
the interface device; the SIM card responds with Answer to Reset. Although the SIM interface has no
defined requirements, the ISO/IEC 7816 defines reset and power-down sequences (for detailed
information see ISO/IEC 7816).
Table 73. PWM Output Timing Parameter
Ref No.
Parameter
Minimum
Maximum
Unit
1
System CLK frequency1
1 CL of PWMO = 30 pF
0
ipg_clk
MHz
2a
Clock high time
12.29
ns
2b
Clock low time
9.91
ns
3a
Clock fall time
0.5
ns
3b
Clock rise time
0.5
ns
4a
Output delay time
9.37
ns
4b
Output setup time
8.71
ns
4a
PWM Source Clock
2a
1
PWM Output
2b
3a
3b
4b
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