參數(shù)資料
型號: MCIMX258CJM4A
廠商: Freescale Semiconductor
文件頁數(shù): 129/153頁
文件大?。?/td> 0K
描述: IC MPU IMX25 IND 400MAPBGA
標準包裝: 90
系列: i.MX25
核心處理器: ARM9
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,CAN,EBI/EMI,以太網,I²C,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 128
程序存儲器類型: 外部程序存儲器
RAM 容量: 144K x 8
電壓 - 電源 (Vcc/Vdd): 1.15 V ~ 1.52 V
數(shù)據(jù)轉換器: A/D 3x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 400-LFBGA
包裝: 托盤
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10
Freescale Semiconductor
77
WE32A(
muxed
A/D
CS[x] valid to Address Invalid
WE4 – WE7 + (LBN + LBA + 1
– CSA2)
–3 + (LBN + LBA +
1 – CSA)
—ns
WE33
CS[x] Valid to RW Valid
WE8 – WE6 + (RWA – CSA)
3 + (RWA – CSA)
ns
WE34
RW Invalid to CS[x] Invalid
WE7 – WE9 + (RWN – CSN)
3 – (RWN_CSN)
ns
WE35
CS[x] Valid to OE Valid
WE10 – WE6 + (OEA – CSA)
3 + (OEA – CSA)
ns
WE35A
(muxed
A/D)
CS[x] Valid to OE Valid
WE10 – WE6 + (OEA + LBN +
LBA + LAH + 1 – CSA)
–3 + (OEA + LBN
+ LBA + LAH + 1 –
CSA)
3 + (OEA + LBN +
LBA + LAH + 1 –
CSA)
ns
WE36
OE Invalid to CS[x] Invalid
WE7 – WE11 + (OEN – CSN)
3 – (OEN – CSN)
ns
WE37
CS[x] Valid to EB[y] Valid (Read
access)
WE12 – WE6 + (EBRA – CSA)
3 + (EBRA4 – CSA)
ns
WE38
EB[y] Invalid to CS[x] Invalid
(Read access)
WE7 – WE13 + (EBRN – CSN)
3 – (EBRN5 – CSN)
ns
WE39
CS[x] Valid to LBA Valid
WE14 – WE6 + (LBA – CSA)
3 + (LBA – CSA)
ns
WE40
LBA Invalid to CS[x] Invalid
WE7 – WE15 – CSN
3 – CSN
ns
WE40A
(muxed
A/D)
CS[x] Valid to LBA Invalid
WE14 – WE6 + (LBN + LBA + 1
– CSA)
–3 + (LBN + LBA +
1 – CSA)
3 + (LBN + LBA + 1 –
CSA)
ns
WE41
CS[x] Valid to Output Data Valid
WE16 – WE6 – CSA
3 – CSA
ns
WE41A
(muxed
A/D)
CS[x] Valid to Output Data Valid WE16 – WE6 + (LBN + LBA +
LAH + 1 – CSA)
3 + (LBN + LBA +
LAH + 1 – CSA)
ns
WE42
Output Data Invalid to CS[x]
Invalid
WE17 – WE7 – CSN
3 – CSN
ns
WE43
Input Data Valid to CS[x]
Invalid
MAXCO – MAXCSO + MAXDI
MAXCO6 –
MAXCSO7 +
MAXDI8
—ns
WE44
CS[x] Invalid to Input Data
invalid
00
ns
WE45
CS[x] Valid to EB[y] Valid
(Write access)
WE12 – WE6 + (EBWA – CSA)
3 + (EBWA – CSA)
ns
WE46
EB[y] Invalid to CS[x] Invalid
(Write access)
WE7 – WE13 + (EBWN – CSN)
–3 + (EBWN – CSN)
ns
WE47
DTACK Valid to CS[x] Invalid
MAXCO – MAXCSO + MAXDTI
MAXCO6
MAXCSO7 +
MAXDTI9
—ns
WE48
CS[x] Invalid to DTACK invalid
0
ns
Table 57. WEIM Asynchronous Timing Parameters Relative to Chip Select Table (continued)
Ref No.
Parameter
Determination By
Synchronous Measured
Parameters1
Min
Max
(If 133 MHz is
supported by SoC)
Unit
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