參數(shù)資料
型號： MCIMX27MJP4A
廠商： Freescale Semiconductor
文件頁數(shù)： 24/152頁
文件大?。?/td> 0K
描述： MPU IMX27 473-MAPBGA
產(chǎn)品培訓(xùn)模塊： i.MX27 Multimedia Application Processor
標(biāo)準(zhǔn)包裝： 84
系列： i.MX27
核心處理器： ARM9
芯體尺寸： 32-位
速度： 400MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，I²C，MMC，智能卡，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，LCD，POR，PWM，WDT
程序存儲器類型： ROMless
RAM 容量： 45K x 8
電壓 - 電源 (Vcc/Vdd)： 1.38 V ~ 1.52 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 473-LFBGA
包裝： 托盤
i.MX27 and i.MX27L Data Sheet, Rev. 1.8
12
Freescale Semiconductor
Functional Description and Application Information
Included in the AUDMUX are two types of interfaces. The internal ports connect to the processor serial
interfaces, and the external ports connect to off-chip audio devices and serial interfaces of other processors.
A desired connectivity is achieved by configuring the appropriate internal and external ports.
The module includes full 6-wire SSI interfaces for asynchronous receive and transmit, as well as a
configurable 4-wire (synchronous) or 6-wire (asynchronous) peripheral interface. The AUDMUX allows
each host interface to be connected to any other host or peripheral interface in a point-to-point or
point-to-multipoint (network mode).
2.3.7
Clock and Reset Module (CRM)
The Clock and Reset Module (CRM) generates clock and reset signals used throughout the
i.MX27/MX27L processor and for external peripherals. It also enables system software to control,
customize, or read the status of the following functions:
Chip ID
Multiplexing of I/O signals
I/O Driving Strength
I/O Pull Enable Control
Well-Bias Control
System boot mode selection
DPTC Control
2.3.8
CMOS Sensor Interface (CSI)
The CMOS Sensor Interface (CSI) is a logic interface that enables the i.MX27/MX27L processors to
connect directly to external CMOS sensors and CCIR656 video source.
The capabilities of the CSI include the following:
Configurable interface logic to support popular CMOS sensors in the market
Support traditional sensor timing interface
Support CCIR656 video interface, progressive mode for smart sensor, interlace mode for PAL and
NTSC input
8-bit input port for YCC, YUV, Bayer, or RGB data
32
× 32 FIFO storing image data supporting Core data read and DMA data burst transfer to system
memory
Full control of 8-bit and 16-bit data to 32-bit FIFO packing
Direct interface to eMMA-lt Pre-Processing block (PrP) - Not available on the i.MX27L
Single interrupt source to interrupt controller from maskable sensor interrupt sources: Start of
Frame, End of Frame, Change of Field, FIFO full
Configurable master clock frequency output to sensor
Asynchronous input logic design. Sensor master clock can be driven by either the i.MX27/MX27L
processor or by external clock source.
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