參數(shù)資料
型號(hào): MCIMX31DVMN5D
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 532 MHz, MICROPROCESSOR, PBGA473
封裝: 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-473
文件頁數(shù): 59/118頁
文件大?。?/td> 1083K
代理商: MCIMX31DVMN5D
Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
45
Figure 33. SDRAM Read Cycle Timing Diagram
Table 33. DDR/SDR SDRAM Read Cycle Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
SD1
SDRAM clock high-level width
tCH
3.4
4.1
ns
SD2
SDRAM clock low-level width
tCL
3.4
4.1
ns
SD3
SDRAM clock cycle time
tCK
7.5
ns
SD4
CS, RAS, CAS, WE, DQM, CKE setup time
tCMS
2.0
ns
SD5
CS, RAS, CAS, WE, DQM, CKE hold time
tCMH
1.8
ns
SD6
Address setup time
tAS
2.0
ns
SD7
Address hold time
tAH
1.8
ns
SD8
SDRAM access time
tAC
6.47
ns
SDCLK
WE
ADDR
DQ
DQM
COL/BA
Data
CS
CAS
RAS
Note: CKE is high during the read/write cycle.
SD4
SD1
SD3
SD2
SD4
SD5
SD6
SD7
SD10
SD8
SD9
SDCLK
ROW/BA
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