參數(shù)資料
型號: MCIMX31LCVMN4DR2
廠商: Freescale Semiconductor
文件頁數(shù): 64/108頁
文件大?。?/td> 0K
描述: IC MPU I.MX31L AUTO 473MAPBGA
標準包裝: 750
系列: i.MX31
核心處理器: ARM11
芯體尺寸: 32-位
速度: 400MHz
連通性: 1 線,ATA,EBI/EMI,F(xiàn)IR,I²C,MMC/SD,PCMCIA,SIM,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,LCD,POR,PWM,WDT
程序存儲器類型: ROMless
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.22 V ~ 3.3 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 473-LFBGA
包裝: 帶卷 (TR)
Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor
59
4.3.15.4
Synchronous Interface to Dual-Port Smart Displays
Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are
identical to parameters of the synchronous interface. See Section 4.3.15.2.2, “Interface to Active Matrix
4.3.15.4.1
Interface to a TV Encoder, Functional Description
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits
D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively. Figure 50 depicts the
interface timing,
The frequency of the clock DISPB_D3_CLK is 27 MHz (within 10%).
The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low.
The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal.
It remains low for a single clock cycle.
The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC
signal. It remains low for at least one clock cycle.
— At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC
and DISPB_D3_HSYNC coincide.
— At a transition to an even field (of the same frame), they do not coincide.
The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC
signal being high.
Table 46. Sharp Synchronous Display Interface Timing Parameters—Pixel Level
ID
Parameter
Symbol
Value
Units
IP21
SPL rise time
Tsplr
(BGXP – 1) * Tdpcp
ns
IP22
CLS rise time
Tclsr
CLS_RISE_DELAY * Tdpcp
ns
IP23
CLS fall time
Tclsf
CLS_FALL_DELAY * Tdpcp
ns
IP24
CLS rise and PS fall time
Tpsf
PS_FALL_DELAY * Tdpcp
ns
IP25
PS rise time
Tpsr
PS_RISE_DELAY * Tdpcp
ns
IP26
REV toggle time
Trev
REV_TOGGLE_DELAY * Tdpcp
ns
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