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參數(shù)資料
| 型號： | MCM63L918A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 9MBit Synchronous Late Write Fast Static RAM(8M位同步遲寫快速靜態(tài)RAM) |
| 中文描述： | 9MBit快速同步后寫入靜態(tài)存儲器（800萬位同步遲寫快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 412K |
| 代理商： | MCM63L918A |
MCM63L836A
MCM63L918A
12
MOTOROLA FAST SRAM
FUNCTIONAL OPERATION
READ AND WRITE OPERATIONS
All control signals are registered on the rising edge of the
CK clock. These signals must meet the setup and hold times
shown in the AC Characteristics table. On the falling edge of
the current cycle, the output latch becomes transparent and
data is available. The output data is latched on the rising
edge of the next clock. The output data is available at the
output at KLQV or KHQV, whichever s ater. KHQV s he nter-
nal latency of the device. During this same cycle, a new read
address can be applied to the address pins.
A write cycle can occur on the next cycle as long as
tKHQZ and tDVKH are met. Read cycles may follow write
cycles immediately.
SS and SW control output drive. Chip deselect via a high
on SS at the rising edge of the CK clock has its effect on the
output drivers immediately. SW low deselects the output driv-
ers immediately (on the same cycle). Output selecting via a
low on SS and high on SW at a rising CK clock has its effect
on the output drivers at tKLQX.
Output data will be valid at tKHQV or tKLQV, which is even
later. Outputs will begin driving at tKLQX1. Outputs will hold
previous data until tKLQX or tKHQZ in the case of a write
following a read.
WRITE AND BYTE WRITE FUNCTIONS
Note that in the following discussion the term “byte” refers
to nine bits of the RAM I/O bus. In all cases, the timing
parameters described for synchronous write input (SW)
apply to each of the byte write enable inputs (SBa, SBb,
etc.).
Byte write enable inputs have no effect on read cycles.
This allows the system designer not interested in performing
byte writes to connect the byte enable inputs to active low
(VSS). Reads of all bytes proceed normally and write cycles,
activated via a low on SW and the rising edge of CK, write
the entire RAM I/O width. This way the designer is spared
having to drive multiple write input buffer loads.
Byte writes are performed using the byte write enable
inputs in conjunction with the synchronous write input (SW).
It is important to note that writing any one byte will inhibit a
read of all bytes at the current address. The RAM can not
simultaneously read one byte and write another at the same
address. A write cycle initiated with none of the byte write
enable inputs active, is neither a read or a write. No write will
occur, but the outputs will be deselected as in a normal write
cycle.
LATE WRITE
The write address is sampled on the first rising edge of
clock, and write data is sampled on the following rising edge.
The late write feature is implemented with single stage
write buffering. Write buffering is transparent to the user. A
comparator monitors the address bus and, when necessary,
routes buffer contents to the outputs to ensure coherent
operation. This occurs in all cases, whether there is a byte
write or a full word is written.
PROGRAMMABLE IMPEDANCE OPERATION
The designer can program the RAMs output buffer imped-
ance by terminating the ZQ pin to VSS through a precision
resistor (RQ). The value of RQ is five times the output imped-
ance desired. For example, 250
resistor will give an output
impedance of 50
.
Impedance updates occur during write and deselect
cycles.
The actual change in the impedance occurs in small incre-
ments and is binary. The binary impedance has 256 values
and therefore, there are no significant disturbances that
occur on the output because of this smooth update method.
At power up, the output impedance will take up to 65,000
cycles for the impedance to be completely updated. At
recovery from sleep mode, the previously programmed value
will be recovered.
POWER UP AND INITIALIZATION
The following supply voltage application sequence is rec-
ommended: VSS, VDD, then VDDQ. Please note, per the
Absolute Maximum Ratings table, VDDQ is not to exceed
VDDQ + 0.5 V or 2.5 V max, whatever the instantaneous
value of VDD. Once supplies have reached specification
levels, a minimum dwell of 1.0 ms with CK clock inputs
cycling is required before beginning normal operations. At
power up the output impedance will be set at approximately
50
as stated above.
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