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參數資料
| 型號： | MCM63L918A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 9MBit Synchronous Late Write Fast Static RAM(8M位同步遲寫快速靜態(tài)RAM) |
| 中文描述： | 9MBit快速同步后寫入靜態(tài)存儲器（800萬位同步遲寫快速靜態(tài)內存） |
| 文件頁數： | 5/20頁 |
| 文件大?。?/td> | 412K |
| 代理商： | MCM63L918A |
MCM63L836A
MCM63L918A
5
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS, See Note)
Rating
Symbol
Value
Unit
Core Supply Voltage
VDD
–0.5 to 3.9
V
Output Supply Voltage
VDDQ
–0.5 to 2.5
V
Voltage On Any Pin Other Than JTAG
Vin
–0.5 to 2.5
V
Voltage On Any JTAG Pin
VJTAG
–0.5 to 3.9
V
Input Current (per I/O)
Iin
±
50
mA
Output Current (per I/O)
Iout
±
25
mA
Operating Temperature
TA
0 to 70
°
C
Temperature Under Bias
Tbias
–10 to 85
°
C
Storage Temperature
Tstg
–55 to 125
°
C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
PBGA PACKAGE THERMAL CHARACTERISTICS
Rating
Symbol
Max
Unit
Notes
Junction to Ambient (Still Air)
R
θ
JA
R
θ
JA
R
θ
JA
R
θ
JB
R
θ
JC
50
°
C/W
1, 2
Junction to Ambient (@200 ft/min)
Single–Layer Board
39
°
C/W
1, 2
Junction to Ambient (@200 ft/min)
Four–Layer Board
27
°
C/W
3
Junction to Board (Bottom)
23
°
C/W
4
Junction to Case (Top)
1
°
C/W
5
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38–87.
3. Measured using a four–layer test board with two internal planes.
4. Indicates the average thermal resistance between the die and the printed circuit board as measured by the ring cold plate method.
5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC–883
Method 1012.1).
CLOCK TRUTH TABLE
K, CLK
ZZ
SS
SW
SBa
SBb
SBc
SBd
DQ (n)
DQ (n+1)
Mode
L – H
L
L
H
X
X
X
X
Dout 0 – 35
High–Z
X
Read Cycle All Bytes
L – H
L
L
L
L
H
H
H
DIn 0 – 8
DIn 9 – 17
DIn 18 – 26
DIn 27 – 35
DIn 0 – 35
High–Z
Write Cycle 1st Byte
L – H
L
L
L
H
L
H
H
High–Z
Write Cycle 2nd Byte
L – H
L
L
L
H
H
L
H
High–Z
Write Cycle 3rd Byte
L – H
L
L
L
H
H
H
L
High–Z
Write Cycle 4th Byte
L – H
L
L
L
L
L
L
L
High–Z
Write Cycle All Bytes
L – H
L
L
L
H
H
H
H
High–Z
Abort Write Cycle
L – H
L
H
X
X
X
X
X
High–Z
X
Deselect Cycle
X
H
X
X
X
X
X
X
High–Z
High–Z
Sleep Mode
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised that
normal precautions be taken to avoid applica-
tion of any voltage higher than maximum rated
voltages to this high–impedance circuit.
This CMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
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