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參數(shù)資料
| 型號： | MCM67A618BFN15 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 64K x 18 Bit Asynchronous/ Latched Address Fast Static RAM |
| 中文描述： | 64K X 18 CACHE TAG SRAM, 15 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 141K |
| 代理商： | MCM67A618BFN15 |
MCM67A618B
2
MOTOROLA FAST SRAM
BLOCK DIAGRAM
A0 – A15
DQ0 – DQ17
MEMORY ARRAY
64K x 18
E
WRITE AMP
OUTPUT
BUFFER
CONTROL
16
18
AL
LW
UW
G
16
18
18
LATCH
DL
18
9
9
LATCH
LATCH
TRUTH TABLE
E
LW
UW
AL*
DL*
G
Mode
Supply
Current
I/O
Status
H
X
X
X
X
X
Deselected Cycle
ISB
ICC
ICC
ICC
ICC
ICC
ICC
ICC
ICC
High–Z
L
X
X
L
X
X
Read or Write Using Latched Addresses
—
L
X
X
H
X
X
Read or Write Using Unlatched Addresses
—
L
H
H
X
X
L
Read Cycle
Data Out
L
H
H
X
X
H
Read Cycle
High–Z
L
L
L
X
L
X
Write Both Bytes Using Latched Data In
High–Z
L
L
L
X
H
X
Write Both Bytes Using Unlatched Data In
High–Z
L
L
H
X
X
X
Write Cycle, Lower Byte
High–Z
L
H
L
X
X
X
Write Cycle, Lower Byte
High–Z
*E and Addresses satisfy the specified setup and hold times for the falling edge of AL. Data–in satisfies the specified setup
*
and hold times for falling edge of DL.
NOTE: This truth table shows the application of each function. Combinations of these functions are valid.
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS = 0)
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
Vin, Vout
– 0.5 to 7.0
V
Voltage Relative to VSS for Any
Pin Except VCC
– 0.5 to VCC + 0.5
V
Output Current (per I/O)
Iout
±
30
mA
Power Dissipation
PD
Tbias
TA
Tstg
1.6
W
Temperature Under Bias
– 10 to + 85
°
C
Ambient Temperature
0 to + 70
°
C
Storage Temperature
– 55 to + 125
°
C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
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