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參數(shù)資料
| 型號： | MCM67A618BFN15 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 64K x 18 Bit Asynchronous/ Latched Address Fast Static RAM |
| 中文描述： | 64K X 18 CACHE TAG SRAM, 15 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 141K |
| 代理商： | MCM67A618BFN15 |
MCM67A618B
6
MOTOROLA FAST SRAM
ASYNCHRONOUS WRITE CYCLE TIMING
(See Notes 1, 2, and 3)
MCM67A618B–10
MCM67A618B–12
MCM67A618B–15
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Times
tAVAV
tAVWH
tAVEH
tAVWL
tAVEL
tDVWH
tDVEH
10
—
12
—
15
—
ns
4
Setup Times:
Address Valid to End of Write
Address Valid to E High
Address Valid to W Low
Address Valid to E Low
DataValid to W High
Data Valid E High
9
9
0
0
5
5
—
—
—
—
—
—
10
10
0
0
6
6
—
—
—
—
—
—
13
13
0
0
7
7
—
—
—
—
—
—
ns
Hold Times:
W High to Address Invalid
E High to Address Invalid
W High to Data Invalid
E High to Data Invalid
tWHAX
tEHAX
tWHDX
tEHDX
tWLWH
tWLWH
tWLEH
tELWH
tELEH
0
0
0
0
—
—
—
—
0
0
0
0
—
—
—
—
0
0
0
0
—
—
—
—
ns
Write Pulse Width: Write Pulse Width (G Low)
Write Pulse Width (G High)
Write Pulse Width
Enable to End of Write
Enable to End of Write
9
8
9
9
9
—
—
—
—
—
10
9
10
10
10
—
—
—
—
—
13
12
13
13
13
—
—
—
—
—
ns
5
6
5, 6
Output Buffer Control: W High to Output Active
W Low to Output High–Z
tWHQX
tWLQZ
3
—
—
5
3
—
—
6
3
—
—
9
ns
7
7, 8
NOTES:
1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW.
2. AL and DL are equal to VIH for all asynchronous cycles.
3. Both Write Enables must be equal to VIH for all address transitions.
4. All write cycle timing is referenced from the last valid address to the first transitioning address.
5. If E goes high coincident with or before W goes high the output will remain in a high impedance state.
6. If E goes low coincident with or after W goes low the output will remain in a high impedance state.
7. Transition is measured
±
500 mV from steady–state voltage with output load of Figure 1b. This parameter is sampled and not 100% tested.
At any given voltage and temperature, tWLQZ is less than tWHQX for a given device.
8. If G goes low coincident with or after W goes low the output will remain in a high impedance state.
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| MCM67A618FN10 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit Asychronous/Latched Address Fast Static RAM |
| MCM67A618FN12 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit Asychronous/Latched Address Fast Static RAM |
| MCM67A618FN15 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit Asychronous/Latched Address Fast Static RAM |
| MCM67B518 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32K x 18 Bit BurstRAM Synchronous Fast Static RAM |
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