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參數(shù)資料
| 型號(hào)： | MCM67M618BFN9 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 64K X 18 CACHE SRAM, 9 ns, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 166K |
| 代理商： | MCM67M618BFN9 |
MCM67M618B
5
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
5%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
3 ns
Output Timing Reference Level
Output Load
. . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
See Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING
(See Notes 1, 3, and 4)
Parameter
Symbol
b l
MCM67M618B–9
MCM67M618B–10
MCM67M618B–12
U i
Unit
Notes
Min
Max
Min
Max
Min
Max
Cycle Time
tKHKH
tKHQV
tGLQV
tKHQX1
tKHQX2
tGLQX
tGHQZ
tKHQZ
tKHKL
tKLKH
tAVKH
tTSVKH
tDVKH
tWVKH
tBAVKH
tEVKH
15
—
16.6
—
20
—
ns
Clock Access Time
—
9
—
10
—
12
ns
5
Output Enable to Output Valid
—
5
—
5
—
6
ns
Clock High to Output Active
6
—
6
—
6
—
ns
Clock High to Output Change
3
—
3
—
3
—
ns
Output Enable to Output Active
0
—
0
—
0
—
ns
Output Disable to Q High–Z
—
6
—
7
—
7
ns
6
Clock High to Q High–Z
3
6
3
7
3
7
ns
6
Clock High Pulse Width
5
—
5
—
6
—
ns
Clock Low Pulse Width
5
—
5
—
6
—
ns
Setup Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
2.5
—
2.5
—
2.5
—
ns
7
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
tKHAX
tKHTSX
tKHDX
tKHWX
tKHBAX
tKHEX
0.5
—
0.5
—
0.5
—
ns
7
NOTES:
1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW.
2. A read cycle is defined by UW and LW high or TSP low for the setup and hold times. A write cycle is defined by LW or UW low and TSP
high for the setup and hold times.
3. All read and write cycle timings are referenced from K or G.
4. G is a don’t care when UW or LW is sampled low.
5. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.
6. Transition is measured
±
500 mV from steady-state voltage. This parameter is sampled rather than 100% tested. At any given voltage and
temperature, tKHQZ max is less than tKHQZ1 min for a given device and from device to device.
7. This is a synchronous device. All addresses must meet the specified setup and hold times for
ALL
rising edges of K whenever TSP or
TSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for
ALL
rising edges
of K when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain
enabled.
Figure 1.Test Load
OUTPUT
Z0 = 50
RL = 50
VL = 1.5 V
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