參數(shù)資料
型號(hào)： MCP18480
廠商： Microchip Technology Inc.
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： -48V Hot Swap Controller
中文描述： - 48V熱插拔控制器
文件頁(yè)數(shù)： 47/64頁(yè)
文件大?。?/td> 871K
代理商： MCP18480
2003 Microchip Technology Inc.
DS20091B-page 47
MCP18480
6.8.6
LATCH BLOCK
A current limit latch circuit determines whether, follow-
ing the timeout period resulting from an over-current
condition, the external FET should be latched-off until
reactivated by an external signal, or be allowed to
restart automatically following the timer cycle.
If the RESTART input is low, the part will restart and the
gate drive to the external MOSFET will be restored
automatically. If the RESTART pin is high, a current
limit event will turn the FET off after the programmed
delay and maintain an off condition until the ENABLE
6.8.7
GATE DRIVE BLOCK
The GATE drive block sources a current equal to the
voltage at CLFB divided by 1 k
to the gate of the
external MOSFET. So the current sourced from the
GATE pin is determined by the V
DS
of the external FET.
This current, and the external capacitors around the
FET,
control the slew rate of the drain of the external
FET, limiting the current that would otherwise have to
be diverted from other boards on the backplane. In the
event of a problem (Overvoltage, Undervoltage or cur-
rent
limit), the gate of the external FET is pulled down
with 60 mA.
During normal operation, the GATE pin
ramps up to about 12V, sending the external FET
deeply into the triode region. If the drain current
becomes excessive while the drain-to-source voltage
is high, the inverting input of the op amp is driven to the
CLFB voltage by the current-limiting block, causing a
reduction in the drive to the external FET to reduce the
current through it. This foldback current-limit remains
active until the voltage on C
TIMER
reaches V
REFIN
/2,
after which the GATE output pin is pulled to V
NEG
for
the duration of the timeout period, or until ENABLE is
cycled low momentarily.
For applications in which it is undesirable to have the
drain current track the V
DS
of the external pass FET in
current limit, the user can tie the V
FB
pin to the V
REF
or
V
NEG
pin. This will make the MCP18480 try to force the
drain current to 12 mV/R
SENSE
or 50 mV/R
SENSE
,
respectively, until the TIMER block times out. If fold-
back current-limiting is not desired at all, set the divider
associated with the CL pin to detect the desired current
in order to shut off the GATE immediately.
A voltage on the GATE pin higher than about 8V is one
condition for the PWRGOOD pin to be asserted. Any
fault condition that causes the GATE pin voltage to be
pulled to V
NEG
deasserts the PWRGOOD pin. On
startup, a NMOS transistor with a resistor pulling its
gate up holds the GATE pin down until the MCP18480
is properly biased.
6.8.8
BIAS BLOCK
The internal voltage generation or bias block generates
the biasing currents for all internal blocks. It also pro-
vides a 2.5V reference voltage that is brought out to the
V
REFOUT
pin. This output pin is usually fed back into the
V
REFIN
pin. However, an externally-generated 2.5V
reference voltage may be directly connected to the
V
REFIN
pin, while leaving the V
REFOUT
pin uncon-
nected. A V
REFIN
/2 voltage is generated within the bias
block, which is used as reference in the other blocks.
A internal shunt regulator limits the internal circuitry to
12V. An external current-limiting resistor in series with
V
POS
absorbs the excess voltage. The resulting regu-
lated 12V source is used in the gate drive block and
PWRGOOD output circuit.
The 12V source is also stepped-down to generate a 5V
regulated source. Most of the other circuitry and blocks
operate with the internally-generated 5V.
EQUATION 6-10:
EXTERNAL R
ISET
CURRENT
6.8.9
POWER GOOD BLOCK
The “power good” block monitors the state of the OV
active, the UV active, the current limit circuitry, and out-
put of the FET good block to generate the PWRGOOD
output signal.
I
RISET
V
R
ISET
------------------
-----------2
±
=
Note:
The direction of the current is depen-
dant on where the external R
ISET
resis-
tor is connected (the I
SET
pin to either
the V
NEG
pin or the V
REFIN
pin).
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