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參數(shù)資料
| 型號(hào)： | MCP25055-I/P |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 32/66頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER CAN 8B 14DIP |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 接口： | 1 線，CAN |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 無(wú) |
| 頻率 - 時(shí)鐘： | 4MHz |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 14-PDIP |
| 包裝： | 管件 |
| 包括： | ADC，存儲(chǔ)器，PWM |
| 產(chǎn)品目錄頁(yè)面： | 685 (CN2011-ZH PDF) |
| 配用： | DV250501-ND - KIT DEV CAN MCP250XX |
| 其它名稱： | MCP25055I/P |
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MCP2502X/5X
DS21664D-page 38
2007 Microchip Technology Inc.
6.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
PWMnDCH and TnCON registers. Up to 10-bit
resolution is available. The PWMnDCH contains the
eight MSb’s, while the TnCON register contains the two
LSb’s.
This
10-bit
value
is
represented
by
PWM1DCH:T1CON<1:0> for PWM Module 1 and
PWM2DCH:T2CON<1:0> for PWM Module 2.
The following equation is used to calculate the PMW
duty cycle:
PWMnDCH can be written to at any time, but the duty
cycle value is not latched into PWMnDBH until after a
match between PRn and TMRn occurs (i.e., the period
is complete).
The PWMnDBH register and 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the PWMnDBH and 2-bit latch match TMRn
concatenated with an internal 2-bit Q clock or 2 bits of
the TMRn prescaler, the PWM output pin is cleared.
Maximum PWM resolution (bits) for a given PWM
frequency is equal to:
In order to achieve higher resolution, the PWM
frequency must be decreased. In order to achieve
higher PWM frequency, the resolution must be
decreased. Table 6-1 lists example PWM frequencies
and resolutions for FOSC = 20 MHz. TMRn prescaler
and PRn values are also shown.
TABLE 6-1:
PWM FREQUENCIES AND RESOLUTIONS AT 20 MHZ
REGISTER 6-1:
PWM1 DUTY CYCLE REGISTER MSB (PWM1DCH)
REGISTER 6-2:
PWM2 DUTY CYCLE REGISTER MSB (PWM2DCH)
PWMDC
PWMnDC
()
=*T
OSC*TMRn (prescale)
Note:
If the PWM duty cycle value is longer than
the
PWM
period
(PWM
duty
cycle
= 100%), the PWM output pin will not be
cleared.
log F
OSC
() Fpwm
()
() log 2
()bits
()
PWM Frequency
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.30 kHz 208.30 kHz
Timer Prescaler (1, 4, 16)
16
41111
PRn Value
0xFF
0x3F
0x1F
0x17
Maximum Resolution (bits)
10
8
7
5.5
R/W-x
DC1B9
DC1B8
DC1B7
DC1B6
DC1B5
DC1B4
DC1B3
DC1B2
bit 7
bit 0
bit 7-0
DC1B9:DC1B2: Most Significant PWM0 Duty Cycle bits
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
R/W-x
DC2B9
DC2B8
DC2B7
DC2B6
DC2B5
DC2B4
DC2B3
DC2B2
bit 7
bit 0
bit 7-0
DC2B9:DC2B2: Most Significant PWM2 Duty Cycle bits
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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