參數(shù)資料
型號(hào)： MCP25055-I/P
廠商： Microchip Technology
文件頁(yè)數(shù)： 44/66頁(yè)
文件大小： 0K
描述： IC I/O EXPANDER CAN 8B 14DIP
標(biāo)準(zhǔn)包裝： 30
接口： 1 線，CAN
輸入/輸出數(shù)： 8
中斷輸出： 無(wú)
頻率 - 時(shí)鐘： 4MHz
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 14-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 14-PDIP
包裝： 管件
包括： ADC，存儲(chǔ)器，PWM
產(chǎn)品目錄頁(yè)面： 685 (CN2011-ZH PDF)
配用： DV250501-ND - KIT DEV CAN MCP250XX
其它名稱： MCP25055I/P
2007 Microchip Technology Inc.
DS21664D-page 49
MCP2502X/5X
FIGURE 8-3:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
8.4.2
POWER-UP TIMER
The Power-up Timer (PWRT) provides a fixed, 72 ms
nominal time-out, on power-up only, from the POR. The
Power-up Timer operates on an internal RC oscillator,
with the device being kept in reset as long as the PWRT
is active. The PWRT's time delay allows VDD to rise to
an acceptable level. The power-up time delay will vary
from device to device due to VDD, temperature and
process variation. For more information, please see
8.5
Oscillator Start-up Timer
The Oscillator Start-up Timer (OST) provides a 512
oscillator cycle (TOSC) delay after the PWRT delay is
complete. This ensures that the crystal oscillator has
started and stabilized and must be less than the total
time it takes (704 oscillator cycles or 44 TQ) for the
minimum standard data frame or remote transmit
message to be completed on the CAN bus once a
wake-up from SLEEP occurs. The OST time-out is
invoked only on Power-on Reset or wake-up from
SLEEP.
8.6
Power-down Mode (SLEEP)
Power-down mode (or SLEEP) is enabled via the
SLPEN bit in the OPTREG2 register. When enabled,
the MCP2502X/5X will enter SLEEP once the CAN bus
has been idle for a minimum 1408 bit times while in
Normal mode.
Additionally, the device may be configured to enter
SLEEP while in Listen-only mode immediately after
power-up if there is no activity on the CAN bus.
Subsequent CAN bus activity will wake the device up
from SLEEP and the NEXT message will be confirmed
as a valid message before entering Normal mode. This
feature is enabled via the PUSLP bit in the OPTREG2
register.
While in SLEEP, the I/O ports maintain the status they
had before the SLEEP instruction was executed
(driving high, low or hi-impedance).
The following operations will not function while the
device is in SLEEP:
A/D Module data conversion
Auto-conversion mode
Auto-messaging
PWM module and outputs
Clock output
8.6.1
WAKE-UP FROM SLEEP
The MCP2502X/5X can wake-up from SLEEP through
one of the following events:
External reset input on RST pin
Transmit-on-change due to edge detected on
GPIO pin
Activity detected on CAN bus
For the device to wake-up due to a GPIO transmit-on-
change, the corresponding interrupt enable bit must be
set (enabled). Wake-up occurs regardless of the state
of the GIE bit.
If a wake-up from SLEEP is caused by activity on the
CAN bus, the message that caused the wake-up will not
be received or acknowledged by the MCP2502X/5X.
RST
VDD
OSC1
VDD Rise
Detect
Power-on Reset
OST
10-bit Ripple Counter
PWRT
On-chip
RC OSC
Enable PWRT
Enable OST
S
Q
Chip Reset
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