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參數(shù)資料
| 型號： | MCP455SB |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 400000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 13.56 MHz讀/寫無源RFID器件 |
| 文件頁數(shù)： | 32/50頁 |
| 文件大?。?/td> | 1172K |
| 代理商： | MCP455SB |
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MCRF450/451/452/455
DS40232H-page 32
2003 Microchip Technology Inc.
7.0
MEMORY SECTION
The memory section is organized into two groups: Main
Memory Section and Stored CRC (SCRC) Memory
Section.
7.1
Main Memory Section
The main section is organized into 32 blocks, as shown
in Table 7-1, with each block having 32 bits. Each
individual block can be read and written by the Interro-
gator’s command. The first Blocks (0-2) are used for
predefined parameters and device operation. The next
three Blocks (3-5) are used as the FRF data.
The Blocks from 3 to 31 (29 blocks) are used for user
data memory. Bits from 0 to 15 of Block 0 also can be
used for user memory. The memory is read or written in
32-bit selectable units. The exceptions are the FR bit
and the TF bit of Block 0, which are individually
selectable.
Each block is accessed by the Interrogator’s command
based on block address. The reading of FRF blocks
(Blocks 3-5) can be accomplished in two different
ways: (1) by FRR command or (2) by Read Block
command. The device sends the FRF data when it
receives the FRR command. The length of the FRF
data for the FRR command is determined by DF bits
(see Table 7-6).
7.2
Stored CRC (SCRC) Memory
Section
This memory section is used to store the CRC of the
main memory section. It is organized into 32 blocks.
Each block has 16 bits and contains the CRC of the
corresponding memory block.
The Stored CRC (SCRC) is the CRC of the Interroga-
tor’s writing command (Write command + block
address + data). The device stores the received
Interrogator’s CRC and sends back verification when it
sends the block data. For the Block 0 and 2, the device
sends CCRC instead of the SCRC. The device sends
the CRC of each block as follows:
Blocks 0 and 2: CCRC of block number and block
data.
Other blocks except Block 0 and 2: SCRC.
CRC for FRR response: CCRC of Tag ID and FRF
(Blocks 3-5) data. The data length of the FRF is
determined by DF bits (B0: 26-27).
TABLE 7-1:
MEMORY ORGANIZATION
Main Memory Section
(32 blocks x 32 bits)
Stored CRC Section
(32 blocks x 16 bits)
Comments
M
S
B
L
S
B
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
F
R
T
F
T
F
T
D
F
M
T
T
M
Available to user
(21 Bits)
Block 0
(Tag Parameters + User Memory)
Byte 3
Byte 2
Byte 1
Byte 0
Block 1 (Tag ID = Serial Number)
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
Block 2 (Write Protection bits)
(Clear bit 2 to write-protect Block 2)
Fast
Read
Field
(LS Block)
Block 3 (FR Field Least Significant
Block)
Fast
Read
Field
Block 4 (FR Field)
Fast
Read
Field
(MS Block)
Block 5 (FR Field Most Significant
Block)
Block 6 (User Data)
Block 7 (User Data)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Block 31 (User Data)
相關(guān)PDF資料 |
PDF描述 |
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| MCP455SN | 400000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| MCP455W | 13.56 MHz Read/Write Passive RFID Device |
| MCP455X | 13.56 MHz Read/Write Passive RFID Device |
| MCP452WFB | 13.56 MHz Read/Write Passive RFID Device |
| MCP6001E | 200000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
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