參數(shù)資料
型號： MCP455SB
廠商： Microchip Technology Inc.
英文描述： 400000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
中文描述： 13.56 MHz讀/寫無源RFID器件
文件頁數(shù)： 36/50頁
文件大?。?/td> 1172K
代理商： MCP455SB
MCRF450/451/452/455
DS40232H-page 36
2003 Microchip Technology Inc.
9.0
EXAMPLES
EXAMPLE 9-1:
READ/WRITE PULSE SEQUENCE
t
To write 1 block (32 bits) in Normal mode with TS = 1: ~ 78.014 ms
To read 1 block (32 bits) in Normal mode with TS = 1: ~ 42.214 ms
FRR or FRB Command
(5 gap pulses = 1.575 ms)
Interrogator
Command
Tag Response
(FR response)
Interrogator
Command
(MC and
Read/Write)
Tag Response
(to Read/Write)
Interrogator
Command
(End Process)
Tag Response
to End Process
For FRR Response:
(Preamble (8 bits) + TC (3 bits) + TP (4 bits) + ‘
0
’ + 32 bits of Tag ID
+ FRF (32-96 bits) + CCRC of Tag ID and FRF data
= 160 bits max = 2.286 ms)
For FRB Response:
(Preamble (8 bits) + ‘
00001
’ + ‘
000
’ + 32-bit Tag ID (Block 1 data)
= 64 bits = 0.914 ms)
+ SCRC (16 bits)
Listening window (T
LW
) for 1 ms
t
T
DECODE
(1.225 ms)
Time Slot
(TS)
Matching Code during listening window:
MC code = Calibration pulse (1 symbol) + Matched Tag ID (8 bits)
+ MC code type (3 bits) + 1 Parity bit
= Cal. pulse (1 symbol) + 12 bits = 4 symbols = 11.2 ms
t
For Reading: Cal. pulse (1 symbol) + Read Command (MSN first)
+ Address (MSN first + Parity) = Cal. pulse + 3 symbols = 11.2 ms
For Writing: Cal. pulse (1 symbol) + Write Command (MSN first)
+ Address (MSN first) + data (LSN first) + Parity/CRC (LSN first)
= Cal. pulse (1 symbol) + 14 symbols = 42 ms
Twrite
for EEPROM
(5 ms)
t
Device Outputs:
After a completion of write cycle:
Preamble (8 bits) + written block # (5 bits) + ‘
000
’
+ written block data (32 bits) + CCRC/SCRC (16 bits)
= 64 bits = 0.914 ms
After Read command:
Preamble (8 bits) + block # (5 bits) + ‘
000
’ + block data (32 bits)
+ CCRC/SCRC (16 bits)
= 64 bits = 0.914 ms
t
t
End Process Command:
Cal. pulse + End Process Command (‘
111
’)
+ Address (‘
01010
’) + Parity (1)
= Cal. Pulse + 3 symbols = 11.2 ms
Device Response: 8-bit preamble (‘
11111110
’)
(0.114 ms)
(FRR or FRB)
相關(guān)PDF資料
PDF描述
MCP455SN 400000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
MCP455W 13.56 MHz Read/Write Passive RFID Device
MCP455X 13.56 MHz Read/Write Passive RFID Device
MCP452WFB 13.56 MHz Read/Write Passive RFID Device
MCP6001E 200000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
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