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| 型號： | MCP4706A0T-E/MAY |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 30/86頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT NV EEP I2C 6DFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | EEPROM，I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.1W |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-VDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 6-DFN（2x2） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
| 其它名稱： | MCP4706A0T-E/MAYDKR |
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MCP4706/4716/4726
DS22272C-page 36
2011-2012 Microchip Technology Inc.
4.2
DAC’s (Resistor Ladder)
Reference Voltage
The device can be configured to use one of three
voltage sources for the resistor ladder’s reference
1.
VDD pin voltage
2.
VREF pin voltage internally buffered
3.
VREF pin voltage unbuffered
The selection of the voltage is specified with the volatile
are nonvolatile and volatile VREF1:VREF0 Configuration
bits. On a POR/BOR event, the state of the nonvolatile
VREF1:VREF0 Configuration bits are latched into the
volatile VREF1:VREF0 Configuration bits.
When the user selects the VDD as reference, the VREF
pin voltage is not connected to the resistor ladder.
If the VREF pin is selected, then select between the
Buffered or Unbuffered mode.
In Unbuffered mode, the VREF pin voltage may be from
VSS to VDD.
In Buffered mode, the VREF pin voltage may be from
0.01V to VDD-0.04V. The input buffer (amplifier) pro-
vides low offset voltage, low noise, and a very high
input impedance, with only minor limitations on the
input range and frequency response.
FIGURE 4-2:
Resistor Ladder Reference
Voltage Selection Block Diagram.
4.3
Resistor Ladder
The resistor ladder is a digital potentiometer with the B
Terminal internally grounded and the A terminal
connected to the selected reference voltage (see
Figure 4-3). The volatile DAC register controls the
wiper position. The wiper voltage (VW) is proportional to
the DAC register value divided by the number of
resistor elements (RS) in the ladder (256, 1024, or
4096) related to the VRL voltage.
The resistor ladder (RRL) has a typical impedance of
approximately 210 k
Ω. This resistor ladder resistance
(RRL) may vary from device to device up to ±20%.
Since this is a voltage divider configuration, the actual
RRL resistance does not effect the output given a fixed
voltage at VRL.
If the unbuffered VREF pin is used as the VRL voltage
source, this voltage source should have a low output
impedance.
When the DAC is powered down, the resistor ladder is
disconnected from the selected reference voltage.
FIGURE 4-3:
Resistor Ladder.
Note:
In Unbuffered mode, the voltage source
should have a low output impedance. If
the voltage source has a high output
impedance, then the voltage on the
VREF’s pin would be lower than expected.
The
resistor
ladder
has
a
typical
impedance of 210 k
Ω and a typical
capacitance of 29 pF.
Note:
Any variation or noises on the reference
source can directly affect the DAC output.
The reference voltage needs to be as
clean as possible for accurate DAC
performance.
VRL
VDD
Buffer
R
e
fere
nc
e
VREF1:VREF0
Se
le
c
ti
o
n
VREF
Note:
The maximum wiper position is 2n - 1,
while the number of resistors in the
resistor ladder is 2n. This means that
when the DAC register is at full scale,
there
is
one
resistor
element
(RS)
between the wiper and the VRL voltage.
RS(2n)
RS(2n - 1)
RS(2n - 2)
RS(1)
2n - 1
2n - 2
1
0
RRL
VRL
VW
DAC
Register
VW =
* VRL
DAC Register Value
# Resistors in Resistor Ladder
Where:
# Resistors in Resistor Ladder = 256 (MCP4706)
1024 (MCP4716)
4096 (MCP4726)
PD1:PD0
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