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參數(shù)資料
| 型號(hào)： | MCP4725A2T-E/CH |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 5/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT EE W/I2C SOT23-6 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | EEPROM，I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-6 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 673 (CN2011-ZH PDF) |
| 配用： | MCP4725DM-PTPLS-ND - BOARD DAUGHTER PICTAIL MCP4725 |
| 其它名稱： | MCP4725A2T-E/CHDKR |
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2009 Microchip Technology Inc.
DS22039D-page 13
MCP4725
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
3.1
Analog Output Voltage (VOUT)
VOUT is an analog output voltage from the DAC device.
DAC output amplifier drives this pin with a range of VSS
to VDD.
3.2
Supply Voltage (VDD or VSS)
VDD is the power supply pin for the device. The voltage
at the VDD pin is used as the supply input as well as the
DAC reference input. The power supply at the VDD pin
should be clean as possible for a good DAC
performance.
This pin requires an appropriate bypass capacitor of
about 0.1 F (ceramic) to ground. An additional 10 F
capacitor (tantalum) in parallel is also recommended to
further attenuate high frequency noise present in
application boards. The supply voltage (VDD) must be
maintained in the 2.7V to 5.5V range for specified
operation.
VSS is the ground pin and the current return path of the
device. The user must connect the VSS pin to a ground
plane through a low impedance connection. If an
analog ground path is available in the application PCB
(printed circuit board), it is highly recommended that
the VSS pin be tied to the analog ground path or
isolated within an analog ground plane of the circuit
board.
3.3
Serial Data Pin (SDA)
SDA is the serial data pin of the I2C interface. The SDA
pin is used to write or read the DAC register and
EEPROM data. The SDA pin is an open-drain N-chan
nel driver. Therefore, it needs a pull-up resistor from the
VDD line to the SDA pin. Except for START and STOP
conditions, the data on the SDA pin must be stable
during the high period of the clock. The high or low
state of the SDA pin can only change when the clock
signal on the SCL pin is low. Refer to Section 7.0 “I2C
Serial Interface Communication” for more details of
I2C Serial Interface communication.
3.4
Serial Clock Pin (SCL)
SCL is the serial clock pin of the I2C interface. The
MCP4725 acts only as a slave and the SCL pin accepts
only external serial clocks. The input data from the
Master device is shifted into the SDA pin on the rising
edges of the SCL clock and output from the MCP4725
occurs at the falling edges of the SCL clock. The SCL
pin is an open-drain N-channel driver. Therefore, it
needs a pull-up resistor from the VDD line to the SCL
pin. Refer to Section 7.0 “I2C Serial Interface Com-
communication.
3.5
Device Address Selection Pin (A0)
This pin is used to select the A0 address bit by the user.
The user can tie this pin to VSS (logic ‘0’), or VDD
(logic ‘1’), or can be actively driven by the digital logic
“Device Addressing” for more details of the address
bits.
TABLE 3-1:
PIN FUNCTION TABLE
MCP4725
Name
Description
SOT-23
1VOUT
Analog Output Voltage
2VSS
Ground Reference
3VDD
Supply Voltage
4SDA
I2C Serial Data
5SCL
I2C Serial Clock Input
6A0
I2C Address Bit Selection pin (A0 bit). This pin can be tied to VSS or VDD, or can be
actively driven by the digital logic levels. The logic state of this pin determines what
the A0 bit of the I2C address bits should be.
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