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參數(shù)資料
| 型號： | MCP6033T-E/MS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 8/34頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP SNGL 1.8V W/CS 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.004 V/µs |
| 增益帶寬積： | 10kHz |
| 電流 - 輸入偏壓： | 1pA |
| 電壓 - 輸入偏移： | 150µV |
| 電流 - 電源： | 0.9µA |
| 電流 - 輸出 / 通道： | 23mA |
| 電壓 - 電源，單路/雙路(±)： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MCP6033T-E/MSTR |
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MCP6031/2/3/4
DS22041B-page 16
2008 Microchip Technology Inc.
4.6
Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single-supply) should have a local
bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm
for good high frequency performance. It can use a bulk
capacitor (i.e., 1 F or larger) within 100 mm to provide
large, slow currents. This bulk capacitor can be shared
with other analog parts.
4.7
Unused Op Amps
An unused op amp in a quad package (MCP6034)
should be configured as shown in Figure 4-5. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
FIGURE 4-5:
Unused Op Amps.
4.8
PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012
Ω. A 5V difference would
cause 5 pA of current to flow; which is greater than the
MCP6031/2/3/4
family’s
bias
current
at
+25°C
(±1.0 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
FIGURE 4-6:
Example Guard Ring Layout
for Inverting Gain.
1.
Non-inverting Gain and Unity-Gain Buffer:
a.
Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b.
Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
2.
Inverting Gain and Transimpedance Gain Ampli-
fiers (convert current to voltage, such as photo
detectors):
a.
Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b.
Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
VDD
MCP6034 (A)
MCP6034 (B)
R1
R2
VDD
VREF
V
REF
V
DD
R
2
R
1
R
2
+
------------------
=
Guard Ring
VIN–VIN+
VSS
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