參數(shù)資料
型號： MCP6409-H/SL
廠商： Microchip Technology
文件頁數(shù)： 9/44頁
文件大小： 0K
描述： IC OPAMP QUAD 1.8V 1MHZ 14SOIC
標準包裝： 57
放大器類型： 通用
電路數(shù)： 4
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 0.5 V/µs
增益帶寬積： 1MHz
電流 - 輸入偏壓： 1pA
電壓 - 輸入偏移： 4500µV
電流 - 電源： 45µA
電流 - 輸出 / 通道： 15mA
電壓 - 電源，單路/雙路(±)： 1.8 V ~ 6 V
工作溫度： -40°C ~ 150°C
安裝類型： 表面貼裝
封裝/外殼： 14-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 14-SOICN
包裝： 管件
2009-2011 Microchip Technology Inc.
DS22229D-page 17
MCP6401/1R/1U/2/4/6/7/9
4.0
APPLICATION INFORMATION
The MCP6401/1R/1U/2/4/6/7/9 family of op amps is
manufactured using Microchip’s state-of-the-art CMOS
process and is specifically designed for low-power,
high-precision applications.
4.1
Rail-to-Rail Input
4.1.1
PHASE REVERSAL
The MCP6401/1R/1U/2/4/6/7/9 op amps are designed
to prevent phase reversal when the input pins exceed
the supply voltages. Figure 2-33 shows the input
voltage exceeding the supply voltage with no phase
reversal.
4.1.2
INPUT VOLTAGE LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors against many (but not all)
over-voltage conditions, and to minimize the input bias
current (IB).
FIGURE 4-1:
Simplified Analog Input ESD
Structures.
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages that go well above VDD; their
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
over-voltage (beyond VDD) events. Very fast ESD
events (that meet the spec) are limited so that damage
does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs;
Figure 4-2 shows one approach to protecting these
inputs.
FIGURE 4-2:
Protecting the Analog
Inputs.
A significant amount of current can flow out of the
inputs when the Common Mode voltage (VCM) is below
ground (VSS); See Figure 2-35.
4.1.3
INPUT CURRENT LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see
Figure 4-3 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible
currents in or out of the input pins (and the ESD diodes,
D1 and D2). The diode currents will go through either
VDD or VSS.
FIGURE 4-3:
Protecting the Analog
Inputs.
4.1.4
NORMAL OPERATION
The input stage of the MCP6401/1R/1U/2/4/6/7/9 op
amps use two differential input stages in parallel. One
operates at a low Common Mode input voltage (VCM),
while the other operates at a high VCM. With this
topology, the device operates with a VCM up to 300 mV
above VDD and 300 mV below VSS (see Figure 2-14).
The input offset voltage is measured at VCM = VSS –
0.3V and VDD + 0.3V to ensure proper operation.
The transition between the input stages occurs when
VCM is near VDD – 1.1V (see Figures 2-6 and 2-7). For
the best distortion performance and gain linearity, with
non-inverting gains, avoid this region of operation.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage
Bond
Pad
VIN–
V1
VDD
D1
V2
D2
MCP640x
VOUT
U1
V1
R1
VDD
D1
min(R1,R2)>
VSS –min(V1, V2)
2mA
V2
R2
D2
MCP640x
VOUT
U1
min(R1,R2)>
max(V1,V2)– VDD
2mA
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