參數(shù)資料
型號(hào)： MCP6566UT-E/OT
廠商： Microchip Technology
文件頁(yè)數(shù)： 15/30頁(yè)
文件大?。?/td> 0K
描述： IC COMPARATOR O-D 1.8V SOT23-5
產(chǎn)品培訓(xùn)模塊： MCP656x
標(biāo)準(zhǔn)包裝： 1
類型： 通用
元件數(shù)： 1
輸出類型： CMOS，開路漏極
電壓 - 電源，單路/雙路(±)： 1.8 V ~ 5.5 V
電壓 - 輸入偏移（最小值）： 10mV @ 5.5V
電流 - 輸入偏壓（最小值）： 1pA @ 5.5V
電流 - 輸出（標(biāo)準(zhǔn)）： 50mA
電流 - 靜態(tài)（最大值）： 130µA
CMRR, PSRR（標(biāo)準(zhǔn)）： 66dB CMRR，70dB PSRR
傳輸延遲（最大）： 80ns
磁滯： 5mV
工作溫度： -40°C ~ 125°C
封裝/外殼： SC-74A，SOT-753
安裝類型： 表面貼裝
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 681 (CN2011-ZH PDF)
其它名稱： MCP6566UT-E/OTDKR
30
DS580F6
CS8406
SFMT0
SFMT1
4
5
Serial Audio Data Format Select (Input) - Selects the serial audio input port format. See Table 3 on
APMS
10 Serial Audio Data Port Master/Slave Select (
Input
) - APMS should be connected to VL to set serial
audio input port as a master or connected to GND to set the port as a slave.
HWCK0
HWCK1
20
27
OMCK Clock Ratio Select (Input) - Selects the ratio of OMCK to the input sample rate (Fs). A pull-up to
VL or pull-down to GND is required to set the appropriate mode. See Table 4 on page 28.
TCBLD
11 Transmit Channel Status Block Direction (
Input
) - Connect TCBLD to VL to set TCBL as an output.
Connect TCBLD to GND to set TCBL as an input.
TCBL
15
Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during
the first sub-frame of a transmitted channel status block, and low at all other times. When operated as
input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be
the start of a channel status block.
CEN
16
C Bit Enable (Input) - Determines how the channel status data bits are input. When CEN is low, Hard-
ware Mode A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected
channel status data. When CEN is high, Hardware Mode B is selected, where the COPY/C pin is used
to enter serial channel status data.
V
17 Validity Bit (
Input
) - In Hardware Modes A and B, the V pin input determines the state of the validity bit
in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.
U
18 User Data Bit (
Input
) - In Hardware Modes A and B, the U pin input determines the state of the user
data bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.
COPY/C
1
COPY Channel Status Bit/C Bit (Input) - In Hardware Mode A (CEN = 0), the COPY/C and ORIG pins
determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream,
see Table 2 on page 28. In Hardware Mode B, the COPY/C pin becomes the direct C bit input data pin,
which is sampled on both edges of LRCK.
EMPH
3
Pre-Emphasis Indicator (Input) - In Hardware Mode A (CEN = 0), the EMPHpin low sets the 3 empha-
sis channel status bits to indicate 50/15 s pre-emphasis of the transmitted audio data. If EMPH is high,
then the three EMPH channel status bits are set to 000, indicating no pre-emphasis.
AUDIO
19 Audio Channel Status Bit (
Input
) - In Hardware Mode A (CEN = 0), the AUDIO pin determines the
state of the audio/non audio Channel Status bit in the outgoing AES3 data stream.
ORIG
28
ORIG Channel Status Bit Control (Input) - In Hardware Mode A (CEN = 0), the ORIG and COPY/C
pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data
TEST
2
7
8
Test Pins (Input) - These pins are unused inputs. It is recommended that these pins be tied to a supply
(VL or GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left float-
ing, however current consumption from VL will increase by 25 A per TEST pin that is left floating.
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