參數(shù)資料
型號: MCP6566UT-E/OT
廠商: Microchip Technology
文件頁數(shù): 4/30頁
文件大小: 0K
描述: IC COMPARATOR O-D 1.8V SOT23-5
產(chǎn)品培訓(xùn)模塊: MCP656x
標(biāo)準(zhǔn)包裝: 1
類型: 通用
元件數(shù): 1
輸出類型: CMOS,開路漏極
電壓 - 電源,單路/雙路(±): 1.8 V ~ 5.5 V
電壓 - 輸入偏移(最小值): 10mV @ 5.5V
電流 - 輸入偏壓(最小值): 1pA @ 5.5V
電流 - 輸出(標(biāo)準(zhǔn)): 50mA
電流 - 靜態(tài)(最大值): 130µA
CMRR, PSRR(標(biāo)準(zhǔn)): 66dB CMRR,70dB PSRR
傳輸延遲(最大): 80ns
磁滯: 5mV
工作溫度: -40°C ~ 125°C
封裝/外殼: SC-74A,SOT-753
安裝類型: 表面貼裝
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 681 (CN2011-ZH PDF)
其它名稱: MCP6566UT-E/OTDKR
20
DS580F6
CS8406
MMTCS - Select A or B channel status data to transmit in Mono Mode
Default = ‘0’
0 - Use channel A CS data for the A subframe and use channel B CS data for the B subframe
1 - Use the same CS data for both the A and B subframe outputs. If MMTLR = 0, use the left channel CS
data. If MMTLR = 1, use the right channel CS data.
MMTLR - Channel Selection for AES Transmitter Mono Mode
Default = ‘0’
0 - Use left channel input data for consecutive subframe outputs
1- Use right channel input data for consecutive subframe outputs
8.4
Data Flow Control (03h)
The Data Flow Control register configures the flow of audio data. The output data should be muted prior to
changing bits in this register to avoid transients.
TXOFF - AES3 Transmitter Output Driver Control
Default = ‘0
0 - AES3 transmitter output pin drivers normal operation
1 - AES3 transmitter output pin drivers drive to 0 V.
AESBP - AES3 bypass mode selection
Default = ‘0’
0 - Normal operation
1 - Connect the AES3 transmitter driver input di rectly to the RXP pin, which becomes a normal TTL
threshold digital input.
8.5
Clock Source Control (04h)
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control reg-
ister, various Receiver/Transmitter/Transceiver modes may be selected.
RUN - Controls the internal clocks, allowing the CS8406 to be placed in a “powered down” low current con-
sumption, state.
Default = ‘0’
0 - Internal clocks are stopped. Internal state machines are reset. The fully static
control port registers are operational, allowing registers to be read or changed. Reading and
writing the U and C data buffers is not possible. Power consumption is low.
1 - Normal part operation. This bit must be set to 1 to allow the CS8406 to begin operation.
All input clocks should be stable in frequency and phase when RUN is set to 1.
CLK1:0 - Output master clock (OMCK) input frequency to output sample rate (Fs) ratio selector. If these bits
are changed during normal operation, always stop the CS8406 first (RUN = 0), write the new value, then
start the CS8406 (RUN = 1).
7
6
5
432
1
0
0
TXOFF
AESBP
0
7
6
5
432
1
0
0
RUN
CLK1
CLK0
0
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