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參數(shù)資料
| 型號： | MCP7940MT-I/MNY |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 10/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTCC I2C 64B SRAM 8-TDFN |
| 標(biāo)準(zhǔn)包裝： | 3,300 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年，方波輸出，SRAM |
| 存儲(chǔ)容量： | 64B |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-TDFN（2x3） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MCP7940MT-I/MNY-ND MCP7940MT-I/MNYTR |
2010 Microchip Technology Inc.
DS22248A-page 23
MCP4901/4911/4921
5.0
SERIAL INTERFACE
5.1
Overview
The MCP4901/4911/4921 devices are designed to
interface directly with the Serial Peripheral Interface
(SPI) port, which is available on many microcontrollers
and supports Mode 0,0 and Mode 1,1. Commands and
data are sent to the device via the SDI pin, with data
being clocked-in on the rising edge of SCK. The
communications are unidirectional, thus the data
cannot be read out of the MCP4901/4911/4921. The
CS pin must be held low for the duration of a write
command. The write command consists of 16 bits and
is used to configure the DAC’s control and data latches.
Register 5-1 through Register 5-3 detail the input regis-
ter that is used to configure and load the DAC register
for each device. Figure 5-1 through Figure 5-3 show
the write command for each device.
Refer to Figure 1-1 and the SPI Timing Specifications
Table for detailed input and output timing specifications
for both Mode 0,0 and Mode 1,1 operation.
5.2
Write Command
The write command is initiated by driving the CS pin
low, followed by clocking the four Configuration bits and
the 12 data bits into the SDI pin on the rising edge of
SCK. The CS pin is then raised, causing the data to be
latched into the DAC’s input register.
The MCP4901/4911/4921 utilizes a double-buffered
latch structure to allow the analog output to be
synchronized with the LDAC pin, if desired.
By bringing the LDAC pin down to a low state, the con-
tent stored in the DAC’s input register is transferred into
the DAC’s output register (VOUT), and VOUT is updated.
All writes to the MCP4901/4911/4921 devices are
16-bit words. Any clocks past the 16th clock will be
ignored. The Most Significant 4 bits are Configuration
bits. The remaining 12 bits are data bits. No data can
be transferred into the device with CS high. This
transfer will only occur if 16 clocks have been
transferred into the device. If the rising edge of CS
occurs prior to that, shifting of data into the input
register will be aborted.
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