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參數(shù)資料
| 型號(hào)： | MCP79512T-I/MN |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTCC SPI 64B SRAM 10-TDFN |
| 標(biāo)準(zhǔn)包裝： | 3,300 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，EEPROM，閏年，方波輸出，SRAM，唯一 ID |
| 存儲(chǔ)容量： | 64B |
| 時(shí)間格式： | HH:MM:SS:hh（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | SPI |
| 電源電壓： | 1.8 V ~ 3.6 V |
| 電壓 - 電源，電池： | 1.3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-TDFN（3x3） |
| 包裝： | 帶卷 (TR) |
Micrel, Inc.
SY87739L
June 2011
10
M9999-061511
hbwhelp@micrel.com
Accum
Add
Sum
Modulo
Bit
0
5
1
5
10
1
10
5
15
1
15
5
20
1
20
5
25
2
0
2
5
7
1
7
5
12
1
12
5
17
1
17
5
22
1
22
5
27
4
0
4
5
9
1
9
5
14
1
14
5
19
1
19
5
24
1
0
1
5
6
1
6
5
11
1
11
5
16
1
16
5
21
1
21
5
26
3
0
3
5
8
1
8
5
13
1
13
5
18
1
18
5
23
0
or (408) 955-1690
Table 2. 5/23 Example
Note that the sequence of bits in the last column,
reading down, is the optimal pattern to generate.
The choice of repeating bit pattern reduces jitter
because a fractional-N synthesizer relies on edges
temporarily not matching, but averaging out over some
time interval. Anything that reduces the timing disparity
between
edges
arriving
at
the
phase-frequency
comparator will reduce jitter.
Center Frequency Trim
This circuit block generates two identical reference
voltages for the two VCO on the SY87739L. This voltage
pair can be digitally trimmed. Trimming occurs under
control of the acquisition sequencer, which trims for
center frequency of the fractional-N synthesizer only.
The wrapper synthesizer VCO is matched to the
fractional-N VCO. Both VCO are fed the same coarse
adjustment voltage, and so both center nominally at the
same frequency.
An 8-bit counter implements the voltage steps. The
acquisition sequencer steps through this counter, which
changes its voltage by about 12mV per step. The coarse
input to the VCO is nominally set at 500MHz per volt.
The
acquisition
sequencer
exercises
the
center
frequency trim circuit so that the VCO control voltage
ends up within about 12mV of where it should be, were it
exactly centered for the desired output frequency.
Lock Detector
The SY87739L ensures proper operation of both
synthesizers by verifying that both PLL have achieved
lock. The LOCKED output asserts active high only when
this is the case, that is, both PLL are locked.
The SY87739L implements a digital lock detector that is
both simple and robust. Each phase-frequency detector
provides a charge pump output that is the logical OR of
pump up and pump down pulses.
The lock-detect circuit processes this charge pump
output with a pulse width discriminator. Once each
reference clock rising edge, the discriminator will
produce a pulse, only if the phase difference between
the feedback divider and the reference input is too large.
These pulses are subsequently processed digitally. A
PLL that is out of lock, is declared to be in lock only if
256 consecutive reference clocks have NO large phase
errors, as reported by the pulse width discriminator. Any
large phase error event, even a single one, that arrives
before lock is declared, will reset the circuit.
Once in lock, a PLL is declared out of lock if more
large-phase-difference
than
small-phase-difference
events occur that is, if over time, a net of 256 large-
phase-difference events occur. That is accomplished by
counting up when large-phase-difference events occur
and counting down in the case of small-phase events.
Wrapper Synthesizer
The frequency generated by the fractional-N PLL is
further processed by a more classical PLL circuit, as
shown in Figure 3.
Figure 3. Wrapper Architecture
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