參數(shù)資料
型號： MCS7840
廠商： Electronic Theatre Controls, Inc.
英文描述： USB-2.0 to Four Serial Ports
中文描述： 的USB 2.0 4個(gè)串行端口
文件頁數(shù)： 12/41頁
文件大?。?/td> 447K
代理商： MCS7840
MCS7840
USB-2.0 to Four Serial Ports
Page 12
Rev.
1.2
FIFO Control Register (FCR):
The FCR controls the UART behavior in various modes.
Register:
Description:
Offset:
Permissions:
Access Condition:
Default Value:
FCR
FIFO Control Register
2
Write
0x00
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Flush
THR
Bit[1]
Flush
RHR
Bit[0]
Enable
FIFOs
RHR Trigger Level
Reserved
Reserved
Bit
Description
Operation
0
Enable FIFO Mode
Logic 0: Byte Mode
Logic 1: FIFO Mode
Logic 0: No change
Logic 1: Flushes the contents of RHR, This is operative
only in FIFO mode. The RHR is automatically
fl
ushed whenever changing between Byte Mode
and FIFO Mode. The bit will return to zero after
clearing the FIFO.
Logic 0: No change
Logic 1: Flushes the content of the THR, in the same
manner as FCR[1] does the RHR
Reserved
1
Flush RHR
2
Flush THR
3
Reserved
[5:4]
Reserved
Reserved
[7:6]
RHR Trigger Level
See Table Below
In 550 Mode, the receiver FIFO trigger levels are
de
fi
ned by FCR[7:6].
The interrupt trigger level &
fl
ow control trigger level
where appropriate are de
fi
ned by L2 in the table.
L1 de
fi
nes a lower
fl
ow control trigger level. The two
trigger levels used together introduce a hysteresis
element into the hardware RTS/CTS
fl
ow control.
In Byte Mode (450 Mode) trigger levels are all set to 1.
FCR[7:6]
550 Mode (FIFO = 16)
L1
1
1
1
1
L2
1
4
8
14
2’b00
2’b01
2’b10
2’b11
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