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參數(shù)資料
| 型號： | MCZ33099CEG |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Adaptive Alternator Voltage Regulator |
| 中文描述： | 自適應(yīng)發(fā)電機(jī)電壓調(diào)節(jié)器 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 230K |
| 代理商： | MCZ33099CEG |
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
33099
TYPICAL APPLICATIONS
for the V
DD
regulator and activates all other voltage
regulators and bias currents. After engine start, the LRC
mode is activated, independent of the phase frequency or
independent of a Wide Open Throttle condition. When the
battery system voltage increases to V
set
, the regulator
resumes the normal operational mode. After switching the
ignition switch to the OFF position, voltage V
ign
decreases
below voltage V
Tign
, causing the comparator C
ign
to provide
an ignition-OFF signal to the Ignition Delay Circuit. After
phase frequency f
ph
< f
1
due to ignition turn OFF, supply
currents and voltages are reduced in the regulator to provide
the standby drain current drain. However, voltage V
DD
for
logic and voltage V
ref
for reference voltages remain active to
be able to sense an ignition input voltage.
In some applications, the ignition input is connected to the
low side of the fault lamp as shown in
Figure 4
, page
9
. When
the lamp driver circuitry is generating a lamp ON signal, a
lamp polling signal causes the Lamp Drain output to be
periodically GATED OFF. As a result, voltage V
ign
> V
Tign
during the lamp OFF polling period, causing comparator C
ign
to periodically provides an ignition-ON signal to the Ignition
Delay Circuit. During the Lamp On condition, the Ignition
Delay Circuit provides a minimum ignition turn-off delay
(t
id(off)
) such that all currents and regulator voltages remain
ON between the Lamp Off polling pulses.
BATTERY AND ALTERNATOR OUTPUT VOLTAGE
SENSING
The system battery voltage is directly sensed by the
REMOTE input using a remote wire as a Kelvin connection.
The Remote input resistance (R
rem
) at the REMOTE input is
typically 68 k
. The voltage at the Remote Sense input (V
rs
)
is a ratioed value of the Remote voltage (V
rem
). The intended
ratio of V
rem
/ V
rs
is about 7.45. The BAT pin voltage (V
bat
) is
also sensed as an internal Local voltage (V
l
). A Local Sense
voltage (V
ls
) is a ratioed value of voltage V
l
, where the
intended ratio of V
l
/ V
ls
is also 7.45. The Local internal
connection is provided for fault protection against the remote
wire being grounded or exhibiting a high remote wire
resistance due to being disconnected or due to a corrosive or
loose connection. Thus the Local connection ensures that
alternator regulation of the system voltage continues in well-
defined states for all possible Remote input fault conditions.
LOCAL AND REMOTE VOLTAGE PROCESSING
AND SWITCHING
During Remote operation both the external Remote input
connection and internal Local connection senses
approximately the same regulated system voltage of V
set
=
14.8 V. For this case, voltages V
rs
and V
ls
are approximately
2.0 V. Because the remote switching comparator C
rs
is
referenced to 0.6 V, both switches S1 and S2 are OPEN and
remain open when voltage V
rs
> 0.6 V or when voltage V
rem
is greater than the remote loss threshold voltage (V
Trem
).
Voltage V
rs
is coupled to the input of a unity-gain combiner /
buffer CB1. Voltage V
ls
is buffered and coupled to the output
of a unity-gain Local Buffer (LB) and ratioed by the R5 /
(R4+R5) resistor divider to provide an input voltage to a unity-
gain combiner buffer CB2. Thus the voltage at the input of
the combiner CB2 is normally 0.8 V
ls
(or 1.6 V typically),
while voltage V
rs
on the input of CB1 is typically 2.0 V.
Because voltage V
o
reflects the highest voltage at the input
of either combiner, voltage V
o
will be voltage V
rs
in Remote
operation with Remote connected to V
bat
. For this case,
voltage V
rs
is filtered by a 300 Hz low-pass filter and
translated to the FB buffer output. Voltage V
rs
at the FB buffer
output is then compared to a digital-to-analog converter
output voltage ramp (V
dac
) for duty cycle regulation.
During a Remote fault condition when the remote sense
line is OPEN or grounded, voltage V
rs
at the Remote Sense
input will be zero, causing comparator C
rs
to activate
switches S1 and S2 to a CLOSED position. As a result,
voltage V
ls
is coupled through buffer LB directly to the input
of combiner CB2. Because the voltage V
ls
on the input of
combiner CB2 is greater than voltage V
rs
(= 0 V) on the input
of combiner CB1, voltage V
ls
is coupled to the output of the
combiners as voltage V
o
. Thus in this fault case, voltage V
ls
is filtered and translated to the FB buffer output for being
compared to voltage ramp V
dac
for regulation.
During a remote fault condition in which the resistance of
the Remote sense wire increases due to the corrosion or a
loose connection, a finite external remote fault resistance
occurs causing voltage V
rem
to decrease, but voltage V
rem
remains greater than voltage V
Trem
. As a result, switches S1
and S2 remain in an OPEN condition, while the system
voltage will increase due to the effective increase in the
Remote resistor divider ratio. As a result, voltage V
l
increases
until the voltage at the input of combiner CB2 is
approximately 2.0 V, or V
ls
is about 1.2 (2.0 V), or 2.25 V due
to the R4 / R5 divider ratio. Because the local divider ratio
translates voltage V
ls
to V
bat
by about factor 7.4, the final
regulated output voltage for this condition is 7.4 (2.25), or
18.5 V. This is the secondary regulation voltage (V
set2
).
When the system voltage increases to the Overvoltage
Threshold (V
Tov
), a fault indication occurs by the lamp. Thus
this particular Remote fault condition produces a fault
indication, but regulates to prevent an extreme system
overvoltage condition. When the Remote fault resistance
becomes great enough to cause voltage V
rem
< V
Trem
, the
regulated system voltage returns to the local regulation as
described for an OPEN or grounded Remote input.
INTERNAL CLOCK OSCILLATOR AND 8-BIT
COUNTER
An internal clock oscillator is provided having a typical
oscillation frequency (f
osc
) of 101 kHz. The output of the
oscillator is coupled to an 8-bit counter that provides
8 counting bits to the logic and the four most significant
counting bits (MSB) to the LRC circuitry and to a digital-to-
analog converter (DAC) waveform generator. The output
MSB frequency (f
msb
) of the 8-bit divider is about 395 Hz
(f
msb
= f
osc
/ 256), which determines the PWM frequency at
the GATE output. An external LRC TEST pin is provided for
accelerating internal testing of the LRC function and logic.
Under normal operation, the LRC TEST pin is grounded by
an internal 10 k
resistance to ground. Under accelerated
test conditions, the LRC TEST voltage is 5.0 V, and a fourth
bit (f
osc
/16) from the 8-bit divider is used to determine the
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| MCZ33099CEGR2 | 功能描述:線性穩(wěn)壓器 - 標(biāo)準(zhǔn) ALT. VOLT REG 14.6 RoHS:否 制造商:STMicroelectronics 輸出類型: 極性: 輸出電壓:1.8 V 輸出電流:150 mA 負(fù)載調(diào)節(jié): 最大輸入電壓:5.5 V 線路調(diào)整率: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-323-5L |
| MCZ33099EG | 功能描述:線性穩(wěn)壓器 - 標(biāo)準(zhǔn) ALT. VOLT REG 14.8 RoHS:否 制造商:STMicroelectronics 輸出類型: 極性: 輸出電壓:1.8 V 輸出電流:150 mA 負(fù)載調(diào)節(jié): 最大輸入電壓:5.5 V 線路調(diào)整率: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-323-5L |
| MCZ33099EGR2 | 功能描述:線性穩(wěn)壓器 - 標(biāo)準(zhǔn) ALT. VOLT REG 14.8 RoHS:否 制造商:STMicroelectronics 輸出類型: 極性: 輸出電壓:1.8 V 輸出電流:150 mA 負(fù)載調(diào)節(jié): 最大輸入電壓:5.5 V 線路調(diào)整率: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-323-5L |
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