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參數(shù)資料
| 型號(hào)： | MCZ33099CEG |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Adaptive Alternator Voltage Regulator |
| 中文描述： | 自適應(yīng)發(fā)電機(jī)電壓調(diào)節(jié)器 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 230K |
| 代理商： | MCZ33099CEG |
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
33099
TYPICAL APPLICATIONS
PWM GATE frequency. Thus, the rates are accelerated by a
factor of 16.
LOW-PASS FILTER, DAC, AND ANALOG DUTY
CYCLE REGULATOR COMPARATOR
The output voltage V
o
of combiners CB1 and CB2 is
coupled to an input of a 300 Hz low-pass filter (Rf, Cf) to
remove high-frequency components of system noise at V
bat
and thus associated with voltages V
ls
, or V
rs
. The output of
the low-pass filter is coupled to a unity-gain buffer FB that
provides a filter buffer FB output.
The 4 MSBs of the 8-bit counter causes the DAC to
generate a 4-bit 395 Hz voltage waveform having
16 descending 1.75 mV steps, ramping from V
ref
to [V
ref
-
28 mV], where V
ref
is the 2.0 V reference voltage.
An analog duty cycle comparator (C
dc
) compares the DAC
output voltage waveform to the voltage at the FB output (V
fb
).
When voltage V
fb
is less then voltage [V
ref
- 28 mV],
comparator C
dc
outputs a logic [1], for a 100% duty cycle.
When voltage V
fb
is greater than V
ref
, comparator C
dc
outputs a logic [0] for a 0% duty cycle. When (V
ref
-
28 mV) < V
fb
< V
ref
, comparator C
dc
outputs a duty cycle
defined by the High / Low output voltage ratio for each period
(about 2.54 ms) of the DAC output voltage waveform.
BASIC SYSTEM VOLTAGE REGULATION
From a system voltage regulation viewpoint, the voltages
V
rem
and V
l
from the Remote or Local connections,
respectively, are scaled to the Remote Sense and Local
Sense inputs as voltages V
rs
and V
ls
respectively and
transferred to the FB output as voltage V
fb
. Voltage V
fb
is
compared to the DAC output voltage waveform to generate
the ON and OFF time of the analog duty cycle waveform.
When voltage V
fb
is less than V
ref
- 28 mV, the output of
comparator C
dc
is in a high state. This high state propagates
through an AND3 GATE, an OR1 GATE, and an AND4 GATE
to activate switch S3, generating a fully ON or High GATE
drive voltage. When voltage V
fb
is greater than V
ref
, the
output of comparator C
dc
is in a low state. This low state
propagates through the AND3 GATE, the OR1 GATE, and
the AND4 GATE to activate switch S3 to generate a fully OFF
or low GATE drive voltage. Assuming voltage V
ref
is 2.0 V
and V
fb
= V
rs
, and the local or remote input resistive scale
factor is 7.45, the external MOSFET provides a fully ON field
current when the system voltage is less than 7.45
(V
ref
- 28 mV), or 14.6 V.
The field current is also fully OFF
when the system voltage is greater than 7.45 (V
ref
), or
14.9 V. When voltage V
fb
is less than any portion of the DAC
waveform voltage, comparator C
dc
output is high to produce
an ON field current. When voltage V
fb
is greater than any
portion of the DAC waveform voltage, comparator C
dc
output
is low to produce an OFF field current. Thus the system
feedback will regulate the PWM duty cycle of the field current
from 0% to 100% over about a 210 mV system regulation
voltage range (dVreg). The system voltage is centered at
14.8 V, where a 50% duty cycle field current results for an
average system load current, and the duty cycle regulation
frequency is (f
osc
/ 256), or 395 Hz. Since voltage V
ref
has a
negative TC, voltage V
set
will also have a regulation voltage
temperature coefficient (TC
Vreg
) of about -11 mV/ °C.
INPUT PHASE AND FREQUENCY SWITCH
RESPONSE
The phase voltage V
ph
results from the alternator's stator
AC output voltage being applied to the PHASE input pin.
A phase detection threshold voltage (V
Tph
) is approximately
4.0 V due to the 1.25 V phase reference voltage for the phase
comparator (C
ph
) and the 3.22 voltage ratio associated with
the phase input resistor divider. The phase input resistance
(R
ph
) is typically 60 k
. A PHASE FILTER pin is coupled to
the input of Comparator C
ph
, providing for an external phase
filter capacitance when filtering of high frequency phase
noise is desired. A typical value of .003
μ
F to AGND provides
for an input phase 3.0 db roll-off frequency of about 10 kHz.
Comparator C
ph
also provides about 480 mV of hysteresis at
the PHASE input pin. Comparator C
ph
further provides a
phase signal binary output voltage having a phase frequency
of f
ph
and is applied to digital frequency switches F1 and F2.
Switch F1 outputs a logic [1] when frequency f
ph
is less then
phase detection frequency f
1
. Frequency f
1
is equal to
frequency f
msb
/ 8, or 49.3 Hz for a 101 kHz oscillator
frequency. Switch F2 outputs a logic [1] when the frequency
f
ph
is greater then the low/high transition frequency f
2
.
Frequency f
2
is equal to frequency 3f
msb
/4, or 296 Hz for a
101 kHz oscillator frequency. These frequency switches are
used to define the Load Response Control region of
operation, an undervoltage at a high RPM fault condition, and
a low RPM fault condition due to a broken or loose belt.
LOAD RESPONSE CONTROL (LRC)
The LRC circuit consists of a digital duty cycle generator,
an analog/digital (A/D) duty cycle comparator and tracking
circuit, an up/down control switch, an up/down (U/D) counter,
a programmable divider (Np), and a multiplexer (MUX).
During normal operation, the LRC circuit becomes active and
generates digital duty cycle control of the GATE drive when
frequency f
ph
is less than frequency f
2
(f
1
< f
ph
< f
2
). The slow
LRC response becomes inactive and the analog duty cycle
controls the GATE drive when frequency f
ph
is greater than
frequency f
2
(f
1
< f
ph
< f
2
). During initial ignition and initial
engine start, the LRC response is in effect, independent of
frequency f
ph
, until system voltage is regulating at voltage
V
set
.
The digital duty cycle generator receives the 4 MSBs from
the 8-bit counter as input and generates 11 discrete digital
duty cycles on 11 output lines. The frequency of each duty
cycle waveform is about 395 Hz (f
msb
), which results from the
MSB of the 8-bit division of the 101 kHz OSC clock
frequency. The minimum duty cycle on the first output line is
31.25% and the maximum duty cycle on the eleventh output
line is 93.75%. The duty cycle difference between each
incremental duty cycle is 6.25%. All 11 duty cycle generator
output lines are coupled as data inputs to the MUX.
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| MCZ33099CEGR2 | 功能描述:線性穩(wěn)壓器 - 標(biāo)準(zhǔn) ALT. VOLT REG 14.6 RoHS:否 制造商:STMicroelectronics 輸出類型: 極性: 輸出電壓:1.8 V 輸出電流:150 mA 負(fù)載調(diào)節(jié): 最大輸入電壓:5.5 V 線路調(diào)整率: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-323-5L |
| MCZ33099EG | 功能描述:線性穩(wěn)壓器 - 標(biāo)準(zhǔn) ALT. VOLT REG 14.8 RoHS:否 制造商:STMicroelectronics 輸出類型: 極性: 輸出電壓:1.8 V 輸出電流:150 mA 負(fù)載調(diào)節(jié): 最大輸入電壓:5.5 V 線路調(diào)整率: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-323-5L |
| MCZ33099EGR2 | 功能描述:線性穩(wěn)壓器 - 標(biāo)準(zhǔn) ALT. VOLT REG 14.8 RoHS:否 制造商:STMicroelectronics 輸出類型: 極性: 輸出電壓:1.8 V 輸出電流:150 mA 負(fù)載調(diào)節(jié): 最大輸入電壓:5.5 V 線路調(diào)整率: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-323-5L |
| MCZ33198EF | 功能描述:功率驅(qū)動(dòng)器IC CHARGE PUMP IC RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| MCZ33198EFR2 | 功能描述:功率驅(qū)動(dòng)器IC CHARGE PUMP IC RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
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