參數(shù)資料
型號(hào): MCZ33689DEW
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: System Basis Chip with LIN Transceiver
中文描述: 系統(tǒng)基礎(chǔ)芯片的LIN收發(fā)器
文件頁(yè)數(shù): 11/31頁(yè)
文件大?。?/td> 309K
代理商: MCZ33689DEW
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
33689
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
RXD OUTPUT PIN (LIN PHYSICAL LAYER)
Low-Level Output Voltage
I
OUT
1.5 mA
V
OL
0.0
0.9
V
High-Level Output Voltage
I
OUT
250
μ
A
V
OH
3.75
5.25
V
TXD INPUT PIN (LIN PHYSICAL LAYER)
Low-Level Input Voltage
V
IL
1.5
V
High-Level Input Voltage
V
IH
3.5
V
Input Hysteresis
V
INHYS
50
145
300
mV
Pullup Current Source
1.0 V < V
TXD
< 3.5 V
I
PUTXD
-100
- 20
μ
A
LIN PHYSICAL LAYER, TRANSCEIVER
Transceiver Output Voltage
Dominant State, TXD LOW, External Bus Pullup 500
Recessive State, TXD HIGH, I
OUT
= 1.0
μ
A
V
LINDOM
V
LINREC
V
SUP
-1.0
1.4
V
Pullup Resistor to VSUP
In Normal Mode and in Sleep and Stop Modes When Not Disabled by
SPI
R
PU
20
30
47
k
Pullup Current Source
In Sleep and Stop Modes When Pullup Disabled by SPI
I
PULIN
1.3
μ
A
Output Current Shutdown Threshold
I
OUTSD
50
75
150
mA
Leakage Output Current to GND
VS1 and VS2 Disconnected, V
LIN
= 18 V
Recessive State, 8.0 V < V
SUP
< 18 V, 8.0 V < V
LIN
< 18 V
GND Disconnected, V
GND
= V
SUP
, V
LIN
= -18 V
I
BUSLEAK
0.0
-1.0
1.0
3.0
10
20
1.0
μ
A
μ
A
mA
LIN PHYSICAL LAYER, RECEIVER
Receiver Input Threshold Voltage
Dominant State, TXD HIGH, RXD LOW
Recessive State, TXD HIGH, RXD HIGH
Center (V
BUSDOM
- V
BUSREC
) 2
Hysteresis (V
BUSDOM
- V
BUSREC
)
V
BUSDOM
V
BUSREC
V
BUSCNT
V
BUSHYS
0.0
0.6
0.475
0.5
0.4
1.0
0.525
0.175
V
SUP
Bus Wake-Up Threshold
V
BUSWU
0.5
V
SUP
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V
V
SUP
18 V, -
40
°
C
T
A
125
°
C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at T
A
= 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
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