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參數(shù)資料
| 型號(hào)： | MCZ33689DEW |
| 廠(chǎng)商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | System Basis Chip with LIN Transceiver |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片的LIN收發(fā)器 |
| 文件頁(yè)數(shù)： | 15/31頁(yè) |
| 文件大?。?/td> | 309K |
| 代理商： | MCZ33689DEW |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
15
33689
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
LIN PHYSICAL LAYER: RECEIVER CHARACTERISTICS AND WAKE-UP TIMINGS
Propagation Delay LIN to RXD
(24)
Dominant State (LIN LOW to RXD LOW)
Recessive State (LIN HIGH to RXD HIGH)
Symmetry (
t
RDOM
-
t
RREC
)
t
RDOM
t
RREC
t
RSYM
—
—
- 2.0
3.0
3.0
—
6.0
6.0
2.0
μ
s
Bus Wake-Up Deglitcher (Sleep and Stop Modes)
(25)
t
PROPWL
30
70
90
μ
s
Bus Wake-Up Event Reported
From Sleep Mode
(26)
From Stop Mode
(27)
t
WU
t
WU
—
—
30
20
—
—
μ
s
Notes
24.
25.
26.
Measured between LIN signal threshold V
INL
or V
INH
and 50% of RXD signal.
See
Figures 9
and
10
, page
18
.
t
WU
is typically 2 internal clock cycles after a LIN rising edge is detected. In Sleep Mode, the measurement is done without a capacitor
connected to the regulator. The delay is measured between the V
SUP
/2 rising edge of the LIN bus and when V
DD
reaches 3.0 V. The
V
DD
rise time is strongly dependent upon the decoupling capacitor at V
DD
pin. See
Figure 9
, page
18
.
t
WU
is typically 2 internal clock cycles after a LIN rising edge is detected. In Stop Mode, the delay is measured between the V
SUP
/2
rising edge of the LIN bus and the falling edge of the
INT
pin. See
Figure 10
, page
18
.
27.
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V
≤
V
SUP
18 V, - 40
°
C
≤
T
A
≤
125
°
C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at T
A
= 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
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