參數(shù)資料
型號(hào)： MCZ33689DEW
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： System Basis Chip with LIN Transceiver
中文描述： 系統(tǒng)基礎(chǔ)芯片的LIN收發(fā)器
文件頁(yè)數(shù)： 26/31頁(yè)
文件大?。?/td> 309K
代理商： MCZ33689DEW
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
33689
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
SPI Register: Read Control Bits
INTSCR — Register Content Flags or Interrupt Source
The INTSCR bit, as shown in
Table 9
, indicates if the
register contents reflect the flags or an interrupt wake-up
source.
LINWU LINFAIL — LIN Bus Status Flag Bit
This bit indicates a LIN wake-up condition or a LIN
overcurrent/overtemperature in accordance with
Table 10
.
VSOV — Overvoltage Flag Bit, VSUV BATFAIL — Under-
voltage Flag Bit, VDDT — VDD Voltage Regulator Status
Flag Bit, and HSST — High-Side Status Flag Bit
Table 11
indicates the register contents of the following
flags:
VSOV flag is set on an overvoltage condition.
VSUV/BATFAIL flag is set on an undervoltage condition.
VDDT flag is set as pre-warning in case of an
overtemperature condition on the voltage regulator.
HSST flag is set on overtemperature conditions on one of
the high-side outputs.
L2 and L1 — Wake-Up Inputs L2 and L1 Status Flag Bit
The L2 and L1 flags, as shown in
Table 12
, reflect the
status of the L2 and L1 input pins and indicate the wake-up
source.
Table 9. Interrupt Status (D7)
INTSCR
Description
0
SPI word read reflects the flag state
1
SPI word read reflects the interrupt or wake-up
source
Table 10. LIN Bus Status (D6)
LINWU/
LINFAIL
Description
0
No LIN bus wake-up
or
failure
1
LIN bus wake-up occurred or LIN overcurrent
overtemperature
Table 11. Over- and Undervoltage, VDD Voltage Regulator, and High-Side Status Flag Bits (D5, D4, D3, and D2)
VSOV
Description
VSUV/
BATFAIL
Description
VDDT
Description
HSST
Description
0
V
SUP
below 19 V
0
V
SUP
above 6.0 V
0
No overtemperature
0
HS
No overtemperature
1
V
SUP
above 18 V
1
V
SUP
below 6.0 V
1
VDD overtemperature
pre-warning
1
HS1, HS2, or HS3
OFF
(overtemperature)
Table 12. Switch Input Wake-Up and Real Time Status (D1 and D0)
L2
Description
L1
Description
0
L2 input LOW
0
L1 input LOW
1
L2 input HIGH or wake-up by L2
(first register read after wake-up)
1
L1 input HIGH or wake-up by L1
(first register read after wake-up)
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