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參數(shù)資料
| 型號(hào)： | MCZ33989EGR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 16/72頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SYSTEM BASIS CHIP CAN 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 安裝類(lèi)型： | 表面貼裝 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
23
33989
FUNCTIONAL DEVICE OPERATION
RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS
TIM register description. Watchdog can only be cleared within the open window time. An attempt to clear the watchdog in the
closed window will generate a reset. Watchdog is cleared through SPI by addressing the TIM1 register.
RESET PIN DESCRIPTION
A reset output is necessary and available to reset the microcontroller. Modes 1 and 2 are available for the reset pin (please
refer to Table 5 for reset pin operation).
Reset causes when SBC is in mode 1:
VDD1 falling out of range — If VDD1 falls below the reset threshold (parameter RSTTH), the RST pin is pulled low until VDD1
returns to the normal voltage.
Power-on reset — At device power-on or at device wake-up from Sleep mode, the reset is maintained low until VDD1 is within
its operation range.
Watchdog timeout — If watchdog is not cleared, the SBC will pull the reset pin low for the duration of the reset time (parameter
RSTDUR).
In Mode 2, the reset pin is not activated in case of Watchdog timeout. Please refer to Table 6 for more detail.
For debug purposes at 25 °C, the Reset pin can be shorted to 5.0 V because of its internal limited current drive capability.
RESET AND WATCHDOG OPERATION: MODES1 AND 2
Watchdog and Reset functions have two modes of operation:
1. Mode 1
2. Mode 2 (also called Safe mode)
These modes are independent of the SBC modes (Normal, Standby, Sleep, and Stop). Modes 1 and 2 selection is achieved
through the SPI (register MCR, bit SAFE). Default mode after reset is Mode 1.
Table 5 provides Reset and Watchdog output mode
of operation. Two modes (modes 1 and 2) are available and can be selected through the SPI Safe bit. Default operation, after
reset or power-up, is Mode 1.
In both modes reset is active at device power-up and wake-up.
In mode 1–Reset is activated in case of VDD1 fall or watchdog not triggered. WD output is active low as soon as reset goes
low. It remains low as long as the watchdog is not properly re-activated by the SPI.
In mode 2–(Safe mode) Reset is not activated in case of watchdog fault. WD output has the same behavior as in mode 1–The
Watchdog output pin is a push-pull structure driving external components of the application for signal instance of an MCU
wrong operation.
Table 5. Reset and Watchdog Output Operation
Events
Mode
WD Output
Reset Output
Devices Power-up
1 or 2 (Safe Mode)
Low to High
VDD1 Normal Watchdog Properly Triggered
1
High
VDD1 < RSTTH
1
High
Low
Watchdog Timeout Reached
1
Low (Note)
Low
VDD1 Normal Watchdog Properly Triggered
2 (Safe Mode)
High
VDD1 < RSTTH
2 (Safe Mode)
High
Low
Watchdog Timeout Reached
2 (Safe Mode)
Low (Note)
High
Notes
27.
WD stays low until the Watchdog register is properly addressed through SPI.
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